From: Kun Yi <kunyi@google.com>
To: jdelvare@suse.com, linux@roeck-us.net, robh+dt@kernel.org,
mark.rutland@arm.com, supreeth.venkatesh@amd.com
Cc: linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org,
openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org
Subject: [PATCH linux hwmon-next v4 3/3] dt-bindings: (hwmon/sbtsi_tmep) Add SB-TSI hwmon driver bindings
Date: Wed, 2 Dec 2020 08:56:01 -0800 [thread overview]
Message-ID: <20201202165601.1532213-4-kunyi@google.com> (raw)
In-Reply-To: <20201202165601.1532213-1-kunyi@google.com>
Document device tree bindings for AMD SB-TSI emulated temperature
sensor.
Signed-off-by: Kun Yi <kunyi@google.com>
---
.../devicetree/bindings/hwmon/amd,sbtsi.yaml | 54 +++++++++++++++++++
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
new file mode 100644
index 000000000000..446b09f1ce94
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: >
+ Sideband interface Temperature Sensor Interface (SB-TSI) compliant
+ AMD SoC temperature device
+
+maintainers:
+ - Kun Yi <kunyi@google.com>
+ - Supreeth Venkatesh <supreeth.venkatesh@amd.com>
+
+description: |
+ SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible
+ interface that reports AMD SoC's Ttcl (normalized temperature),
+ and resembles a typical 8-pin remote temperature sensor's I2C interface
+ to BMC. The emulated thermal sensor can report temperatures in increments
+ of 0.125 degrees, ranging from 0 to 255.875.
+
+properties:
+ compatible:
+ enum:
+ - amd,sbtsi
+
+ reg:
+ maxItems: 1
+ description: |
+ I2C bus address of the device as specified in Section 6.3.1 of the
+ SoC register reference. The SB-TSI address is normally 98h for socket
+ 0 and 90h for socket 1, but it could vary based on hardware address
+ select pins.
+ \[open source SoC register reference\]
+ https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sbtsi@4c {
+ compatible = "amd,sbtsi";
+ reg = <0x4c>;
+ };
+ };
+...
--
2.29.2.454.gaff20da3a2-goog
next prev parent reply other threads:[~2020-12-02 17:03 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-02 16:55 [PATCH linux hwmon-next v4 0/3] SB-TSI hwmon driver v4 Kun Yi
2020-12-02 16:55 ` [PATCH linux hwmon-next v4 1/3] hwmon: (sbtsi) Add basic support for SB-TSI sensors Kun Yi
2020-12-09 20:13 ` Supreeth Venkatesh
[not found] ` <20201203013748.GA228752@roeck-us.net>
2020-12-03 18:06 ` Chatradhi, Naveen Krishna
2020-12-11 21:57 ` Kun Yi
2020-12-02 16:56 ` [PATCH linux hwmon-next v4 2/3] hwmon: (sbtsi) Add documentation Kun Yi
2020-12-02 16:56 ` Kun Yi [this message]
2020-12-09 20:06 ` [PATCH linux hwmon-next v4 3/3] dt-bindings: (hwmon/sbtsi_tmep) Add SB-TSI hwmon driver bindings Rob Herring
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