From: Zev Weiss <zev@bewilderbeest.net>
To: Joel Stanley <joel@jms.id.au>
Cc: Rob Herring <robh@kernel.org>,
linux-aspeed@lists.ozlabs.org, Zev Weiss <zev@bewilderbeest.net>,
- <devicetree@vger.kernel.org>, Andrew Jeffery <andrew@aj.id.au>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
openbmc@lists.ozlabs.org, linux-kernel@vger.kernel.org,
Lubomir Rintel <lkundrak@v3.sk>, Rob Herring <robh+dt@kernel.org>,
linux-serial@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v6 1/4] dt-bindings: serial: 8250: deprecate aspeed, sirq-polarity-sense
Date: Sun, 11 Apr 2021 22:47:09 -0500 [thread overview]
Message-ID: <20210412034712.16778-2-zev@bewilderbeest.net> (raw)
In-Reply-To: <20210412034712.16778-1-zev@bewilderbeest.net>
This property ties SIRQ polarity to SCU register bits that don't
necessarily have any direct relationship to it; the only use of it was
removed in commit c82bf6e133d3 ("ARM: aspeed: g5: Do not set sirq
polarity").
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/serial/8250.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index f54cae9ff7b2..491b9297432d 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -188,6 +188,7 @@ properties:
offset and bit number to identify how the SIRQ polarity should be
configured. One possible data source is the LPC/eSPI mode bit. Only
applicable to aspeed,ast2500-vuart.
+ deprecated: true
required:
- reg
--
2.31.1
next prev parent reply other threads:[~2021-04-12 3:48 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-12 3:47 [PATCH v6 0/4] serial: 8250_aspeed_vuart: generalized DT properties Zev Weiss
2021-04-12 3:47 ` Zev Weiss [this message]
2021-04-12 3:47 ` [PATCH v6 2/4] serial: 8250_aspeed_vuart: refactor sirq and lpc address setting code Zev Weiss
2021-04-12 3:47 ` [PATCH v6 3/4] serial: 8250_aspeed_vuart: add aspeed, lpc-io-reg and aspeed, lpc-interrupts DT properties Zev Weiss
2021-04-12 23:37 ` [PATCH v6 3/4] serial: 8250_aspeed_vuart: add aspeed, lpc-io-reg and aspeed,lpc-interrupts " Andrew Jeffery
2021-04-15 10:46 ` [PATCH v6 3/4] serial: 8250_aspeed_vuart: add aspeed,lpc-io-reg " Andy Shevchenko
2021-04-12 3:47 ` [PATCH v6 4/4] dt-bindings: serial: 8250: add aspeed, lpc-io-reg and aspeed, lpc-interrupts Zev Weiss
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