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From: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
To: <robh+dt@kernel.org>, <joel@jms.id.au>, <andrew@aj.id.au>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-aspeed@lists.ozlabs.org>, <linux-kernel@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <openbmc@lists.ozlabs.org>
Cc: osk@google.com
Subject: [PATCH v7 5/5] ARM: dts: aspeed: Add uart routing to device tree
Date: Mon, 27 Sep 2021 10:30:53 +0800	[thread overview]
Message-ID: <20210927023053.6728-6-chiawei_wang@aspeedtech.com> (raw)
In-Reply-To: <20210927023053.6728-1-chiawei_wang@aspeedtech.com>

Add LPC uart routing to the device tree for Aspeed SoCs.

Signed-off-by: Oskar Senft <osk@google.com>
Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Tested-by: Lei YU <yulei.sh@bytedance.com>
---
 arch/arm/boot/dts/aspeed-g4.dtsi | 6 ++++++
 arch/arm/boot/dts/aspeed-g5.dtsi | 6 ++++++
 arch/arm/boot/dts/aspeed-g6.dtsi | 6 ++++++
 3 files changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 45a25eb4baa4..f0eb599e90f1 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -382,6 +382,12 @@
 					interrupts = <8>;
 					status = "disabled";
 				};
+
+				uart_routing: uart-routing@9c {
+					compatible = "aspeed,ast2400-uart-routing";
+					reg = <0x9c 0x4>;
+					status = "disabled";
+				};
 			};
 
 			uart2: serial@1e78d000 {
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 8e1d00d8445e..c72f9aa13cea 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -490,6 +490,12 @@
 					#reset-cells = <1>;
 				};
 
+				uart_routing: uart-routing@9c {
+					compatible = "aspeed,ast2500-uart-routing";
+					reg = <0x9c 0x4>;
+					status = "disabled";
+				};
+
 				lhc: lhc@a0 {
 					compatible = "aspeed,ast2500-lhc";
 					reg = <0xa0 0x24 0xc8 0x8>;
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 0d1aae6887cd..136273984b5e 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -550,6 +550,12 @@
 					#reset-cells = <1>;
 				};
 
+				uart_routing: uart-routing@98 {
+					compatible = "aspeed,ast2600-uart-routing";
+					reg = <0x98 0x8>;
+					status = "disabled";
+				};
+
 				ibt: ibt@140 {
 					compatible = "aspeed,ast2600-ibt-bmc";
 					reg = <0x140 0x18>;
-- 
2.17.1


      parent reply	other threads:[~2021-09-27  2:34 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-27  2:30 [PATCH v7 0/5] arm: aspeed: Add UART routing support Chia-Wei Wang
2021-09-27  2:30 ` [PATCH v7 1/5] ARM: dts: aspeed: Drop reg-io-width from LPC nodes Chia-Wei Wang
2021-10-08  4:35   ` Joel Stanley
2021-10-21  6:28     ` Joel Stanley
2021-10-21  6:37       ` ChiaWei Wang
2021-10-21  6:48         ` Joel Stanley
2021-10-21  6:54           ` Joel Stanley
2021-10-21  6:59             ` ChiaWei Wang
2021-09-27  2:30 ` [PATCH v7 2/5] dt-bindings: mfd: aspeed-lpc: Convert to YAML schema Chia-Wei Wang
2021-09-29 22:02   ` Rob Herring
2021-09-30  9:48     ` Lee Jones
2021-09-27  2:30 ` [PATCH v7 3/5] dt-bindings: aspeed: Add UART routing controller Chia-Wei Wang
2021-09-29 22:11   ` Rob Herring
2021-09-30  1:55     ` ChiaWei Wang
2021-09-27  2:30 ` [PATCH v7 4/5] soc: aspeed: Add UART routing support Chia-Wei Wang
2021-10-08  4:47   ` Joel Stanley
2021-09-27  2:30 ` Chia-Wei Wang [this message]

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