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* [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC
@ 2022-09-21  7:44 Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC Joel Stanley
                   ` (3 more replies)
  0 siblings, 4 replies; 7+ messages in thread
From: Joel Stanley @ 2022-09-21  7:44 UTC (permalink / raw)
  To: openbmc; +Cc: Andrew Jeffery, Adriana Kobylak

v3: Fix ast2500 change so it builds
    Add r-b from Andrew to other patches
    Add patch to enable RAM drivers in ast2500 config

v2: Rename property to include size
    Use correct size in printf
    Add patch to enable ECC in p10bmc

I will merge the config change first, but I posted it at the last patch
in the series to keep the numbering the same.

Joel Stanley (4):
  ram/aspeed: Use device tree to configure ECC
  ram/aspeed: Remove ECC config option
  ARM: dts: aspeed: p10bmc: Enable ECC
  config/ast2500: Enable RAM devices

 drivers/ram/aspeed/sdram_ast2500.c | 23 +++++++++++++----------
 drivers/ram/aspeed/sdram_ast2600.c | 19 +++++++++++--------
 arch/arm/dts/ast2600-p10bmc.dts    |  1 +
 configs/evb-ast2500_defconfig      |  1 +
 drivers/ram/aspeed/Kconfig         | 20 --------------------
 5 files changed, 26 insertions(+), 38 deletions(-)

-- 
2.35.1


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC
  2022-09-21  7:44 [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC Joel Stanley
@ 2022-09-21  7:44 ` Joel Stanley
  2022-09-23  6:02   ` Andrew Jeffery
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 2/4] ram/aspeed: Remove ECC config option Joel Stanley
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 7+ messages in thread
From: Joel Stanley @ 2022-09-21  7:44 UTC (permalink / raw)
  To: openbmc; +Cc: Andrew Jeffery, Adriana Kobylak

Instead of configuring ECC based on the build config, use a device tree
property to selectively enable ECC at runtime.

There are two properties:

  aspeed,ecc-enabled;
  aspeed,ecc-size-mb = "512";

The enabled property is a boolean that enables ECC if it is present.

The size is the number of MB that should be covered by ECC. Setting it
to zero, or omitting it, defaults the ECC size to "auto detect".

  edac: sdram@1e6e0000 {
    compatible = "aspeed,ast2600-sdram-edac";
    reg = <0x1e6e0000 0x174>;
    interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
    aspeed,ecc-enabled;
    aspeed,ecc-size-mb = "512";
  };

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
v3:
  Fix types for ast2500 case
v2:
  Change property to be aspeed,ecc-size-mb
  Fix printing of size to use mb
---
 drivers/ram/aspeed/sdram_ast2500.c | 19 +++++++++++++------
 drivers/ram/aspeed/sdram_ast2600.c | 14 ++++++++++----
 drivers/ram/aspeed/Kconfig         | 13 -------------
 3 files changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c
index 435e1a8cfc1d..79760975be44 100644
--- a/drivers/ram/aspeed/sdram_ast2500.c
+++ b/drivers/ram/aspeed/sdram_ast2500.c
@@ -279,16 +279,16 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info)
 }
 
 #ifdef CONFIG_ASPEED_ECC
-static void ast2500_sdrammc_ecc_enable(struct dram_info *info)
+static void ast2500_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 {
 	struct ast2500_sdrammc_regs *regs = info->regs;
 	size_t conf_size;
 	u32 reg;
 	
-	conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB;
+	conf_size = conf_size_mb * SDRAM_SIZE_1MB;
 	if (conf_size > info->info.size) {
 		printf("warning: ECC configured %dMB but actual size is %dMB\n",
-		       CONFIG_ASPEED_ECC_SIZE,
+		       conf_size_mb,
 		       info->info.size / SDRAM_SIZE_1MB);
 		conf_size = info->info.size;
 	} else if (conf_size == 0) {
@@ -315,8 +315,9 @@ static void ast2500_sdrammc_ecc_enable(struct dram_info *info)
 }
 #endif
 
-static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
+static int ast2500_sdrammc_init_ddr4(struct udevice *dev)
 {
+	struct dram_info *info = dev_get_priv(dev);
 	int i;
 	const u32 power_control = SDRAM_PCR_CKE_EN
 	    | (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
@@ -371,8 +372,14 @@ static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
 	writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
 
 #ifdef CONFIG_ASPEED_ECC
-	ast2500_sdrammc_ecc_enable(info);
+	if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
+		u32 ecc_size;
+
+		ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
+		ast2500_sdrammc_ecc_enable(info, ecc_size);
+	}
 #endif
+
 	/* Enable all requests except video & display */
 	writel(SDRAM_REQ_USB20_EHCI1
 	       | SDRAM_REQ_USB20_EHCI2
@@ -477,7 +484,7 @@ static int ast2500_sdrammc_probe(struct udevice *dev)
 
 	ast2500_sdrammc_init_phy(priv->phy);
 	if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
-		ast2500_sdrammc_init_ddr4(priv);
+		ast2500_sdrammc_init_ddr4(dev);
 	} else {
 		debug("Unsupported DRAM3\n");
 		return -EINVAL;
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 5118b14f8708..2a4d6af57eb3 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -860,16 +860,16 @@ static void ast2600_sdrammc_update_size(struct dram_info *info)
 	info->info.size = hw_size;
 }
 #ifdef CONFIG_ASPEED_ECC
-static void ast2600_sdrammc_ecc_enable(struct dram_info *info)
+static void ast2600_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 {
 	struct ast2600_sdrammc_regs *regs = info->regs;
 	size_t conf_size;
 	u32 reg;
 
-	conf_size = CONFIG_ASPEED_ECC_SIZE * SDRAM_SIZE_1MB;
+	conf_size = conf_size_mb * SDRAM_SIZE_1MB;
 	if (conf_size > info->info.size) {
 		printf("warning: ECC configured %dMB but actual size is %dMB\n",
-		       CONFIG_ASPEED_ECC_SIZE,
+		       conf_size_mb,
 		       info->info.size / SDRAM_SIZE_1MB);
 		conf_size = info->info.size;
 	} else if (conf_size == 0) {
@@ -989,8 +989,14 @@ L_ast2600_sdramphy_train:
 #endif
 
 #ifdef CONFIG_ASPEED_ECC
-	ast2600_sdrammc_ecc_enable(priv);
+	if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
+		u32 ecc_size;
+
+		ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
+		ast2600_sdrammc_ecc_enable(priv, ecc_size);
+	}
 #endif
+
 	setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK);
 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
 	ast2600_sdrammc_lock(priv);
diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig
index 924e82b19430..54c7769b5bbe 100644
--- a/drivers/ram/aspeed/Kconfig
+++ b/drivers/ram/aspeed/Kconfig
@@ -51,19 +51,6 @@ config ASPEED_ECC
 	help
 	  enable SDRAM ECC function
 
-if ASPEED_ECC
-config ASPEED_ECC_SIZE
-	int "ECC size: 0=driver auto-caluated"
-	depends on ASPEED_ECC
-	default 0
-	help
-	  SDRAM size with the error correcting code enabled. The unit is 
-	  in Megabytes.  Noted that only the 8/9 of the configured size 
-	  can be used by the system.  The remaining 1/9 will be used by 
-	  the ECC engine.  If the size is set to 0, the sdram driver will 
-	  calculate the SDRAM size and set the whole range be ECC enabled.
-endif
-
 choice
 	prompt "DDR4 PHY side ODT"
 	default ASPEED_DDR4_PHY_ODT40
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH u-boot v2019.04-aspeed-openbmc v3 2/4] ram/aspeed: Remove ECC config option
  2022-09-21  7:44 [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC Joel Stanley
@ 2022-09-21  7:44 ` Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 3/4] ARM: dts: aspeed: p10bmc: Enable ECC Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices Joel Stanley
  3 siblings, 0 replies; 7+ messages in thread
From: Joel Stanley @ 2022-09-21  7:44 UTC (permalink / raw)
  To: openbmc; +Cc: Andrew Jeffery, Adriana Kobylak

Always build the code now that it is enabled by device tree.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 drivers/ram/aspeed/sdram_ast2500.c | 4 ----
 drivers/ram/aspeed/sdram_ast2600.c | 5 +----
 drivers/ram/aspeed/Kconfig         | 7 -------
 3 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/drivers/ram/aspeed/sdram_ast2500.c b/drivers/ram/aspeed/sdram_ast2500.c
index 79760975be44..c8eee32da698 100644
--- a/drivers/ram/aspeed/sdram_ast2500.c
+++ b/drivers/ram/aspeed/sdram_ast2500.c
@@ -278,7 +278,6 @@ static void ast2500_sdrammc_calc_size(struct dram_info *info)
 			 << SDRAM_CONF_CAP_SHIFT));
 }
 
-#ifdef CONFIG_ASPEED_ECC
 static void ast2500_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 {
 	struct ast2500_sdrammc_regs *regs = info->regs;
@@ -313,7 +312,6 @@ static void ast2500_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 	writel(0x400, &regs->ecc_test_ctrl);
 	printf("ECC enable, ");
 }
-#endif
 
 static int ast2500_sdrammc_init_ddr4(struct udevice *dev)
 {
@@ -371,14 +369,12 @@ static int ast2500_sdrammc_init_ddr4(struct udevice *dev)
 
 	writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
 
-#ifdef CONFIG_ASPEED_ECC
 	if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
 		u32 ecc_size;
 
 		ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
 		ast2500_sdrammc_ecc_enable(info, ecc_size);
 	}
-#endif
 
 	/* Enable all requests except video & display */
 	writel(SDRAM_REQ_USB20_EHCI1
diff --git a/drivers/ram/aspeed/sdram_ast2600.c b/drivers/ram/aspeed/sdram_ast2600.c
index 2a4d6af57eb3..5f7b160faddf 100644
--- a/drivers/ram/aspeed/sdram_ast2600.c
+++ b/drivers/ram/aspeed/sdram_ast2600.c
@@ -859,7 +859,7 @@ static void ast2600_sdrammc_update_size(struct dram_info *info)
 
 	info->info.size = hw_size;
 }
-#ifdef CONFIG_ASPEED_ECC
+
 static void ast2600_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 {
 	struct ast2600_sdrammc_regs *regs = info->regs;
@@ -890,7 +890,6 @@ static void ast2600_sdrammc_ecc_enable(struct dram_info *info, u32 conf_size_mb)
 	writel(BIT(31), &regs->intr_ctrl);
 	writel(0, &regs->intr_ctrl);
 }
-#endif
 
 static int ast2600_sdrammc_probe(struct udevice *dev)
 {
@@ -988,14 +987,12 @@ L_ast2600_sdramphy_train:
 	}
 #endif
 
-#ifdef CONFIG_ASPEED_ECC
 	if (dev_read_bool(dev, "aspeed,ecc-enabled")) {
 		u32 ecc_size;
 
 		ecc_size = dev_read_u32_default(dev, "aspeed,ecc-size-mb", 0);
 		ast2600_sdrammc_ecc_enable(priv, ecc_size);
 	}
-#endif
 
 	setbits_le32(priv->scu + AST_SCU_HANDSHAKE, SCU_HANDSHAKE_MASK);
 	clrbits_le32(&regs->intr_ctrl, MCR50_RESET_ALL_INTR);
diff --git a/drivers/ram/aspeed/Kconfig b/drivers/ram/aspeed/Kconfig
index 54c7769b5bbe..25238bf28d32 100644
--- a/drivers/ram/aspeed/Kconfig
+++ b/drivers/ram/aspeed/Kconfig
@@ -44,13 +44,6 @@ config ASPEED_BYPASS_SELFTEST
 	  Say Y here to bypass DRAM self test to speed up the boot time
 endif
 
-config ASPEED_ECC
-	bool "aspeed SDRAM error correcting code"
-	depends on DM && OF_CONTROL && ARCH_ASPEED
-	default n
-	help
-	  enable SDRAM ECC function
-
 choice
 	prompt "DDR4 PHY side ODT"
 	default ASPEED_DDR4_PHY_ODT40
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH u-boot v2019.04-aspeed-openbmc v3 3/4] ARM: dts: aspeed: p10bmc: Enable ECC
  2022-09-21  7:44 [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 2/4] ram/aspeed: Remove ECC config option Joel Stanley
@ 2022-09-21  7:44 ` Joel Stanley
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices Joel Stanley
  3 siblings, 0 replies; 7+ messages in thread
From: Joel Stanley @ 2022-09-21  7:44 UTC (permalink / raw)
  To: openbmc; +Cc: Andrew Jeffery, Adriana Kobylak

Enable ECC to cover the entire DRAM by not setting the size property.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 arch/arm/dts/ast2600-p10bmc.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/ast2600-p10bmc.dts b/arch/arm/dts/ast2600-p10bmc.dts
index 23e3bd8ecfbd..1d0f88bf9628 100755
--- a/arch/arm/dts/ast2600-p10bmc.dts
+++ b/arch/arm/dts/ast2600-p10bmc.dts
@@ -41,6 +41,7 @@
 
 &sdrammc {
 	clock-frequency = <400000000>;
+	aspeed,ecc-enabled;
 };
 
 &wdt2 {
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices
  2022-09-21  7:44 [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC Joel Stanley
                   ` (2 preceding siblings ...)
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 3/4] ARM: dts: aspeed: p10bmc: Enable ECC Joel Stanley
@ 2022-09-21  7:44 ` Joel Stanley
  2022-09-23  6:03   ` Andrew Jeffery
  3 siblings, 1 reply; 7+ messages in thread
From: Joel Stanley @ 2022-09-21  7:44 UTC (permalink / raw)
  To: openbmc; +Cc: Andrew Jeffery, Adriana Kobylak

While the ASPEED RAM driver builds unconditionally, without selecting
the CONFIG_RAM symbol it does not load.

Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 configs/evb-ast2500_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/evb-ast2500_defconfig b/configs/evb-ast2500_defconfig
index b83c315e5057..d2a4e835dd12 100644
--- a/configs/evb-ast2500_defconfig
+++ b/configs/evb-ast2500_defconfig
@@ -64,6 +64,7 @@ CONFIG_PHY_GIGE=y
 CONFIG_FTGMAC100=y
 CONFIG_PHY=y
 CONFIG_PINCTRL=y
+CONFIG_RAM=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_SPI=y
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 7+ messages in thread

* Re: [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC Joel Stanley
@ 2022-09-23  6:02   ` Andrew Jeffery
  0 siblings, 0 replies; 7+ messages in thread
From: Andrew Jeffery @ 2022-09-23  6:02 UTC (permalink / raw)
  To: Joel Stanley, openbmc; +Cc: Adriana Kobylak



On Wed, 21 Sep 2022, at 17:14, Joel Stanley wrote:
> Instead of configuring ECC based on the build config, use a device tree
> property to selectively enable ECC at runtime.
>
> There are two properties:
>
>   aspeed,ecc-enabled;
>   aspeed,ecc-size-mb = "512";
>
> The enabled property is a boolean that enables ECC if it is present.
>
> The size is the number of MB that should be covered by ECC. Setting it
> to zero, or omitting it, defaults the ECC size to "auto detect".
>
>   edac: sdram@1e6e0000 {
>     compatible = "aspeed,ast2600-sdram-edac";
>     reg = <0x1e6e0000 0x174>;
>     interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
>     aspeed,ecc-enabled;
>     aspeed,ecc-size-mb = "512";
>   };
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices
  2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices Joel Stanley
@ 2022-09-23  6:03   ` Andrew Jeffery
  0 siblings, 0 replies; 7+ messages in thread
From: Andrew Jeffery @ 2022-09-23  6:03 UTC (permalink / raw)
  To: Joel Stanley, openbmc; +Cc: Adriana Kobylak



On Wed, 21 Sep 2022, at 17:14, Joel Stanley wrote:
> While the ASPEED RAM driver builds unconditionally, without selecting
> the CONFIG_RAM symbol it does not load.
>
> Signed-off-by: Joel Stanley <joel@jms.id.au>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>

^ permalink raw reply	[flat|nested] 7+ messages in thread

end of thread, other threads:[~2022-09-23  6:04 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-21  7:44 [PATCH u-boot v2019.04-aspeed-openbmc v3 0/4] ram: Configure ECC Joel Stanley
2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 1/4] ram/aspeed: Use device tree to configure ECC Joel Stanley
2022-09-23  6:02   ` Andrew Jeffery
2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 2/4] ram/aspeed: Remove ECC config option Joel Stanley
2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 3/4] ARM: dts: aspeed: p10bmc: Enable ECC Joel Stanley
2022-09-21  7:44 ` [PATCH u-boot v2019.04-aspeed-openbmc v3 4/4] config/ast2500: Enable RAM devices Joel Stanley
2022-09-23  6:03   ` Andrew Jeffery

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