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Fri, 16 Jul 2021 14:54:42 +0000 (GMT) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 14.0 $3654.100.0.2.22$) Subject: Re: [PATCH u-boot v2019.04-aspeed-openbmc] aspeed/hace: Reset when error occurs From: Adriana Kobylak In-Reply-To: <20210715045258.13912-1-joel@jms.id.au> Date: Fri, 16 Jul 2021 09:54:41 -0500 Content-Transfer-Encoding: quoted-printable Message-Id: <20A7316B-7A1B-41B3-B5D4-EF9CEA98F279@linux.ibm.com> References: <20210715045258.13912-1-joel@jms.id.au> To: Joel Stanley X-Mailer: Apple Mail (2.3654.100.0.2.22) X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: Dx04poL_OCZmBC5HbxCtpBsgelBJ-HC4 X-Proofpoint-GUID: Dx04poL_OCZmBC5HbxCtpBsgelBJ-HC4 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790 definitions=2021-07-16_05:2021-07-16, 2021-07-16 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 mlxlogscore=999 impostorscore=0 spamscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 adultscore=0 suspectscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2104190000 definitions=main-2107160088 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , OpenBMC Maillist , Adriana Kobylak Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" > On Jul 14, 2021, at 11:52 PM, Joel Stanley wrote: >=20 > Some hasing operations have been triggering an error state. >=20 > This can be reproduced on the u-boot command line: >=20 > hash sha512 83000128 3762a8 >=20 > This completes, and the hash is correct. However HACE1C, the status > register, shows an error bit is set 0x00800000. >=20 > $ bitfield HACE1C 0x00800000 |grep 0x1 > Hash input data buffer overflow: 0x1 >=20 > The next operation is queued, and this never completes. The status > register shows 0x00c00001 >=20 > $ bitfield HACE1C 0x00c00001 |grep 0x1 > Hash input data buffer overflow: 0x1 > Hash input rorate data overflow: 0x1 > Hash engine busy: 0x1 >=20 > A HACE reset will clear this state: >=20 > mw.l 0x1e6e2040 0x10 > mw.l 0x1e6e2044 0x10 >=20 > Adding code to do this if any error bits are set in the status = register > is a workaround for the issue while further debugging is done. >=20 > Another workaround is to do an operation before running the = problematic > operation. This sequence succeeds: >=20 > hash sha512 83000000 10 > hash sha512 83000128 3762a8 >=20 > Signed-off-by: Joel Stanley Tested-by: Adriana Kobylak > --- > drivers/crypto/aspeed_hace.c | 15 ++++++++++++--- > 1 file changed, 12 insertions(+), 3 deletions(-) >=20 > diff --git a/drivers/crypto/aspeed_hace.c = b/drivers/crypto/aspeed_hace.c > index a99fb7c249be..f40779c08816 100644 > --- a/drivers/crypto/aspeed_hace.c > +++ b/drivers/crypto/aspeed_hace.c > @@ -100,9 +100,18 @@ static int digest_object(const void *src, = unsigned int length, void *digest, > writel(HACE_SHA_BE_EN | method, base + ASPEED_HACE_HASH_CMD); >=20 > /* SHA512 hashing appears to have a througput of about 12MB/s */ > - return aspeed_hace_wait_completion(base + ASPEED_HACE_STS, > - HACE_HASH_ISR, > - 1000 + (length >> 3)); > + aspeed_hace_wait_completion(base + ASPEED_HACE_STS, = HACE_HASH_ISR, > + 1000 + (length >> 3)); > + > + if (readl(base + ASPEED_HACE_STS)) { > + debug("\nHACE error 0x%08x, resetting\n", readl(base + = 0x1c)); > + > + writel(0x10, 0x1e6e2040); > + mdelay(5); > + writel(0x10, 0x1e6e2044); > + } > + > + return 0; > } >=20 > void hw_sha1(const unsigned char *pbuf, unsigned int buf_len, > --=20 > 2.32.0 >=20