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Subject: Re: [PATCH v2] ARM: dts: aspeed: rainier: Add N_MODE_VREF gpio
From: Adriana Kobylak <anoo@linux.ibm.com>
In-Reply-To: <CACPK8XfjF+aiEMLocscMEOw8ebKoT2MK8djvv4voyFOBjumXRg@mail.gmail.com>
Date: Tue, 14 Sep 2021 15:44:06 -0500
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References: <20210910195417.2838841-1-anoo@linux.ibm.com>
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To: Joel Stanley <joel@jms.id.au>
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Cc: Matt Spinler <spinler@us.ibm.com>, Derek Howard <derekh@us.ibm.com>,
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> On Sep 14, 2021, at 3:49 AM, Joel Stanley <joel@jms.id.au> wrote:
>=20
> On Fri, 10 Sept 2021 at 19:54, Adriana Kobylak <anoo@linux.ibm.com> wrote:
>>=20
>> From: Adriana Kobylak <anoo@us.ibm.com>
>>=20
>> The N_MODE_VREF gpio is designed to be used to specify how many power
>> supplies the system should have (2 or 4).  If enough power supplies fail
>> so that the system no longer has redundancy (no longer n+1), the
>> hardware will signal to the Onboard Chip Controller that the system may
>> be oversubscribed, and performance may need to be reduced so the system
>> can maintain it's powered on state. This gpio is on a 9552, populate all
>> the gpios on that chip for completeness.
>>=20
>> Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
>> ---
>>=20
>> v2: Update commit message.
>>=20
>> arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 103 +++++++++++++++++++
>> 1 file changed, 103 insertions(+)
>>=20
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boo=
t/dts/aspeed-bmc-ibm-rainier.dts
>> index 6fd3ddf97a21..d5eea86dc260 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
>> @@ -1502,6 +1502,109 @@ eeprom@51 {
>>                reg =3D <0x51>;
>>        };
>>=20
>> +       pca_pres3: pca9552@60 {
>> +               compatible =3D "nxp,pca9552";
>> +               reg =3D <0x60>;
>> +               #address-cells =3D <1>;
>> +               #size-cells =3D <0>;
>> +               gpio-controller;
>> +               #gpio-cells =3D <2>;
>> +
>> +               gpio-line-names =3D
>> +                       "",
>> +                       "APSS_RESET_N",
>> +                       "", "", "", "",
>> +                       "P10_DCM0_PRES",
>> +                       "P10_DCM1_PRES",
>> +                       "", "",
>> +                       "N_MODE_CPU_N",
>> +                       "",
>> +                       "PRESENT_VRM_DCM0_N",
>> +                       "PRESENT_VRM_DCM1_N",
>> +                       "N_MODE_VREF",
>=20
> Should any (all?) of these names be documented?
>=20
> https://github.com/openbmc/docs/blob/master/designs/device-tree-gpio-nami=
ng.md

Not sure. Seems the openbmc doc is documenting the gpios for gpiochip0 only=
? The gpio names for 9552 in this patch come from the System Workbook, and =
doesn=E2=80=99t seem the gpios from the existing 9552 that also come from t=
he System Workbook are documented in the openbmc design doc, such as SLOT6_=
PRSNT_EN_RSVD, SLOT11_EXPANDER_PRSNT_N, etc.

>=20
>=20
>> +                       "";
>> +
>> +               gpio@0 {
>> +                       reg =3D <0>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@1 {
>> +                       reg =3D <1>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@2 {
>> +                       reg =3D <2>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@3 {
>> +                       reg =3D <3>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@4 {
>> +                       reg =3D <4>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@5 {
>> +                       reg =3D <5>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@6 {
>> +                       reg =3D <6>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@7 {
>> +                       reg =3D <7>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@8 {
>> +                       reg =3D <8>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@9 {
>> +                       reg =3D <9>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@10 {
>> +                       reg =3D <10>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@11 {
>> +                       reg =3D <11>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@12 {
>> +                       reg =3D <12>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@13 {
>> +                       reg =3D <13>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@14 {
>> +                       reg =3D <14>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +
>> +               gpio@15 {
>> +                       reg =3D <15>;
>> +                       type =3D <PCA955X_TYPE_GPIO>;
>> +               };
>> +       };
>> +
>>        pca_pres2: pca9552@61 {
>>                compatible =3D "nxp,pca9552";
>>                reg =3D <0x61>;
>> --
>> 2.25.1
>>=20