Re: [PATCH linux dev-4.17 2/7] clk: Aspeed: Add sdhci reset and clock

[Joel Stanley <joel@jms.id.au>]

On 11 July 2018 at 15:17, Ryan Chen <ryanchen.aspeed@gmail.com> wrote:
> 1.Add Aspeed sdhci reset for SCU04 bit 16
> 2.Aspeed sdhci have two clock one is for controller clock,
> another is for SD card clock. so when enable sdhci need enable
> both.
>
> Signed-off-by: Ryan Chen <ryanchen.aspeed@gmail.com>
> ---
>  drivers/clk/clk-aspeed.c                 | 8 +++++++-
>  include/dt-bindings/clock/aspeed-clock.h | 2 +-
>  2 files changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
> index 9e55743..cd1f3b2 100644
> --- a/drivers/clk/clk-aspeed.c
> +++ b/drivers/clk/clk-aspeed.c
> @@ -20,6 +20,7 @@
>
>  #define ASPEED_RESET_CTRL      0x04
>  #define ASPEED_CLK_SELECTION   0x08
> +#define  ASPEED_SDIO_CLK_EN BIT(15)
>  #define ASPEED_CLK_STOP_CTRL   0x0c
>  #define ASPEED_MPLL_PARAM      0x20
>  #define ASPEED_HPLL_PARAM      0x24
> @@ -260,6 +261,11 @@ static int aspeed_clk_enable(struct clk_hw *hw)
>         enval = (gate->flags & CLK_GATE_SET_TO_DISABLE) ? 0 : clk;
>         regmap_update_bits(gate->map, ASPEED_CLK_STOP_CTRL, clk, enval);
>
> +       /* sd ext clk */
> +       if (gate->reset_idx == 16) {
> +               regmap_update_bits(gate->map, ASPEED_CLK_SELECTION, ASPEED_SDIO_CLK_EN, ASPEED_SDIO_CLK_EN);

We do not special case individual clocks. The reset should instead be
added to the aspeed_gates structure above.

In fact, it already is:

        [ASPEED_CLK_GATE_SDCLKCLK] =    { 27, 16, "sdclk-gate",
 NULL,   0 }, /* SDIO/SD */

Although in that table it is 16, and you specify bit 15. The data
sheet I have says SD/SDIO is bit 16.


> +       }
> +
>         if (gate->reset_idx >= 0) {
>                 /* A delay of 10ms is specified by the ASPEED docs */
>                 mdelay(10);
> @@ -317,7 +323,7 @@ static const u8 aspeed_resets[] = {
>         [ASPEED_RESET_PECI]     = 10,
>         [ASPEED_RESET_I2C]      =  2,
>         [ASPEED_RESET_AHB]      =  1,
> -
> +       [ASPEED_RESET_SDHCI]    = 16,
>         /*
>          * SCUD4 resets start at an offset to separate them from
>          * the SCU04 resets.
> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
> index 4476184..088553f 100644
> --- a/include/dt-bindings/clock/aspeed-clock.h
> +++ b/include/dt-bindings/clock/aspeed-clock.h
> @@ -50,5 +50,5 @@
>  #define ASPEED_RESET_I2C               7
>  #define ASPEED_RESET_AHB               8
>  #define ASPEED_RESET_CRT1              9
> -
> +#define ASPEED_RESET_SDHCI             10
>  #endif
> --
> 2.7.4
>