From: Joel Stanley <joel@jms.id.au>
To: Andrew Jeffery <andrew@aj.id.au>
Cc: "open list:GPIO SUBSYSTEM" <linux-gpio@vger.kernel.org>,
Linus Walleij <linus.walleij@linaro.org>,
johnny_huang@aspeedtech.com,
linux-aspeed <linux-aspeed@lists.ozlabs.org>,
OpenBMC Maillist <openbmc@lists.ozlabs.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/3] pinctrl: aspeed: Use the right pinconf mask
Date: Thu, 10 Sep 2020 01:52:36 +0000 [thread overview]
Message-ID: <CACPK8Xe0WqmyXOHdxw=OWbFEzHew7F2aBQ9B5EPRJfDhj=vhmw@mail.gmail.com> (raw)
In-Reply-To: <20200909114312.2863675-3-andrew@aj.id.au>
On Wed, 9 Sep 2020 at 11:43, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> The Aspeed pinconf data structures are split into 'conf' and 'map'
> types, where the 'conf' struct defines which register and bitfield to
> manipulate, while the 'map' struct defines what value to write to
> the register and bitfield.
>
> Both structs have a mask member, and the wrong mask was being used to
> tell the regmap which bits to update.
>
> A todo is to look at whether we can remove the mask from the 'map'
> struct.
>
> Cc: Johnny Huang <johnny_huang@aspeedtech.com>
> Fixes: 5f52c853847f ("pinctrl: aspeed: Use masks to describe pinconf bitfields")
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Owch.
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> index d8972911d505..e03ee78b2434 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> @@ -534,7 +534,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset,
> val = pmap->val << __ffs(pconf->mask);
>
> rc = regmap_update_bits(pdata->scu, pconf->reg,
> - pmap->mask, val);
> + pconf->mask, val);
>
> if (rc < 0)
> return rc;
> --
> 2.25.1
>
next prev parent reply other threads:[~2020-09-10 1:52 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-09 11:43 [PATCH 0/3] pinctrl: aspeed: AST2600 pinconf fixes Andrew Jeffery
2020-09-09 11:43 ` [PATCH 1/3] pinctrl: aspeed: Format pinconf debug consistent with pinmux Andrew Jeffery
2020-09-10 1:52 ` Joel Stanley
2020-09-10 2:15 ` Andrew Jeffery
2020-09-09 11:43 ` [PATCH 2/3] pinctrl: aspeed: Use the right pinconf mask Andrew Jeffery
2020-09-10 1:52 ` Joel Stanley [this message]
2020-09-09 11:43 ` [PATCH 3/3] pinctrl: aspeed-g6: Add bias controls for 1.8V GPIO banks Andrew Jeffery
2020-09-10 2:02 ` Joel Stanley
2020-09-29 12:25 ` [PATCH 0/3] pinctrl: aspeed: AST2600 pinconf fixes Linus Walleij
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