From: Linus Walleij <linus.walleij@linaro.org>
To: "Chia-Wei, Wang" <chiawei_wang@aspeedtech.com>,
Andrew Jeffery <andrew@aj.id.au>
Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>,
Ryan Chen <ryan_chen@aspeedtech.com>,
linux-aspeed <linux-aspeed@lists.ozlabs.org>,
Corey Minyard <minyard@acm.org>,
OpenBMC Maillist <openbmc@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Rob Herring <robh+dt@kernel.org>,
cyrilbur@gmail.com, haiyue.wang@linux.intel.com
Subject: Re: [PATCH 4/4] pinctrl: aspeed-g5: Fix LPC register offsets
Date: Tue, 29 Sep 2020 14:42:22 +0200 [thread overview]
Message-ID: <CACRpkdbn9294JnddMsmGooCe7KCxMiGbuAZ+OAuLwPkZUYD10A@mail.gmail.com> (raw)
In-Reply-To: <20200911034631.8473-5-chiawei_wang@aspeedtech.com>
On Fri, Sep 11, 2020 at 5:47 AM Chia-Wei, Wang
<chiawei_wang@aspeedtech.com> wrote:
> The LPC register offsets are fixed to adapt to the LPC DTS change,
> where the LPC partitioning is removed.
>
> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
I can apply this one patch if I get a review from one of the
Aspeed pinctrl maintainer.
Andrew?
Yours,
Linus Walleij
next prev parent reply other threads:[~2020-09-29 12:48 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-09-11 3:46 [PATCH 0/4] Remove LPC register partitioning Chia-Wei, Wang
2020-09-11 3:46 ` [PATCH 1/4] ARM: dts: Remove LPC BMC and Host partitions Chia-Wei, Wang
2020-09-11 3:46 ` [PATCH 2/4] soc: aspeed: Fix LPC register offsets Chia-Wei, Wang
2020-09-11 3:46 ` [PATCH 3/4] ipmi: kcs: " Chia-Wei, Wang
2020-09-11 3:46 ` [PATCH 4/4] pinctrl: aspeed-g5: " Chia-Wei, Wang
2020-09-29 12:42 ` Linus Walleij [this message]
2020-10-01 0:42 ` Andrew Jeffery
2020-09-11 4:03 ` [PATCH 0/4] Remove LPC register partitioning Joel Stanley
2020-09-11 4:45 ` Andrew Jeffery
2020-09-11 8:21 ` ChiaWei Wang
2020-09-28 7:43 ` Ryan Chen
2020-09-30 6:11 ` Andrew Jeffery
2020-09-30 7:54 ` ChiaWei Wang
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