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From: Peter Maydell <peter.maydell@linaro.org>
Date: Thu, 12 Jul 2018 17:18:37 +0100
Message-ID: <CAFEAcA9Ri8DANtFHtC=H83Vr2zotGRSWOY=QK37MN-TParmETQ@mail.gmail.com>
Subject: Re: [PATCH] aspeed: Implement write-1-{set,
 clear} for AST2500 strapping
To: Andrew Jeffery <andrew@aj.id.au>
Cc: QEMU Developers <qemu-devel@nongnu.org>, Joel Stanley <joel@jms.id.au>, 
 =?UTF-8?Q?C=C3=A9dric_Le_Goater?= <clg@kaod.org>, 
 qemu-arm <qemu-arm@nongnu.org>, OpenBMC Maillist <openbmc@lists.ozlabs.org>
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On 12 July 2018 at 17:10, Andrew Jeffery <andrew@aj.id.au> wrote:
> On Fri, 13 Jul 2018, at 01:28, Peter Maydell wrote:
>> On 9 July 2018 at 15:35, Andrew Jeffery <andrew@aj.id.au> wrote:
>> > The AST2500 SoC family changes the runtime behaviour of the hardware
>> > strapping register (SCU70) to write-1-set/write-1-clear, with
>> > write-1-clear implemented on the "read-only" SoC revision register
>> > (SCU7C). For the the AST2400, the hardware strapping is
>> > runtime-configured with read-modify-write semantics.
>> >
>> > Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
>> > ---
>>
>> Hi -- is this a bugfix suitable for 3.0, or something you'd
>> like to wait until 3.1 ? The commit message sounds like a bugfix...
>
> If we could get it into 3.0 that would be great. I ran into a case where the distinction was important so it would be good to have it resolved sooner rather than later.

No problem -- applied to target-arm.next for 3.0 (should go
in before rc1).

thanks
-- PMM