From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2a00:1450:4864:20::243; helo=mail-lj1-x243.google.com; envelope-from=tali.perry1@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="QG3Swgek"; dkim-atps=neutral Received: from mail-lj1-x243.google.com (mail-lj1-x243.google.com [IPv6:2a00:1450:4864:20::243]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 47MZ833LxDzDqfs for ; Tue, 26 Nov 2019 17:42:08 +1100 (AEDT) Received: by mail-lj1-x243.google.com with SMTP id g3so18785189ljl.11 for ; Mon, 25 Nov 2019 22:42:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=2xGeiyNJPQkdY0veaO9g86+0OzNQfBnLFqQCQNagpdU=; b=QG3Swgek/rSVn1J+AJb0eQMBXhryea3c2QuiaO+V28q6EgpYLHsb/FSuKwITugS0VB DySh6U+r/9XPr18M0z2FAmXGa9Ku1M63aV4vrF5JwDOFw9bx78Lvde/qL3p1U+LDd8nC F6jngmpBqHRYv07nLbTsoiWiyQOIxmYjRP4DekPmIfzftziDwbGOPMYkXa5GDJ3TztbH 9hYkt4Xz73G+oMgGC5xAoSjEY+wGFYHAxPevwwt2hprtxAM/+Ep0AuMOKaOX7wi82p3y koBUQgo/xuWzyrNhUl1pk2DBUf1vj1snYJtWvuwFl8HdBK2mRNFX8b6AeFa5A4WuM2kj yoKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=2xGeiyNJPQkdY0veaO9g86+0OzNQfBnLFqQCQNagpdU=; b=Ku9R/BPmP4rLUQiogQZmVJYuQHknv6dsAambjCmzuUYS/9+2PQ4EuqLp8FEB9Ol5bM OQeRB7t/BmHmOwwv9px3Y8jBzfMA//H5d6aZyxIdAB0pxNNzxSjtEb3siXb/KDFnsxpY Nmbi94E3wz6BzVhFjE46vNEB/sL6Nf2Y3KL4NMgVplHhh6q6TlooHH5NvIY1i9Dyt/YS MeQcSh09/mxfsAxf8eVWdq8kNd1OzvyRkZbLMgAD5pDgRyiw/HzSul+ckoXFal9F45Hv qvViulmrmMnC2N59iJN/nYad2WaBKE4f3Bu9sfu6HuYs0subieGz+YhDNGpbf91gJgSv Ihwg== X-Gm-Message-State: APjAAAWm33s7TXK4Ws0j+keLkIph+QmyTe+XiFm/P8kA5GG1RiroI2+A oZAbOJSka5UMHRXdr4TXOSAzXEdvA3wDrqGavE8= X-Google-Smtp-Source: APXvYqwIAOVTPUbCS11da6ePMgAzGqynOQLLspbm8q5qZ7xv3lHVMqKMZ/3rmZD8ThWCOs+ZieZ5rTxNOvFNUmAPARM= X-Received: by 2002:a05:651c:387:: with SMTP id e7mr25841171ljp.0.1574750523231; Mon, 25 Nov 2019 22:42:03 -0800 (PST) MIME-Version: 1.0 References: <20191121095350.158689-1-tali.perry1@gmail.com> <20191121095350.158689-3-tali.perry1@gmail.com> <20191125151618.GE2412@kunai> In-Reply-To: <20191125151618.GE2412@kunai> From: Tali Perry Date: Tue, 26 Nov 2019 08:47:14 +0200 Message-ID: Subject: Re: [PATCH v7 2/2] i2c: npcm: Add Nuvoton NPCM I2C controller driver To: Wolfram Sang Cc: Rob Herring , Mark Rutland , yuenn@google.com, venture@google.com, benjaminfair@google.com, avifishman70@gmail.com, joel@jms.id.au, Tomer Maimon , syniurge@gmail.com, linux-i2c@vger.kernel.org, OpenBMC Maillist , devicetree , Linux Kernel Mailing List Content-Type: multipart/alternative; boundary="0000000000008c10cc05983a2deb" X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Nov 2019 06:42:12 -0000 --0000000000008c10cc05983a2deb Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Wolfram, Thanks for your comments. The NPCM7XX BMC I2C\SMB controller HW module supports both SMB and I2C. It's main features are: 1. Supports Fast-Mode (400 KHz clock) I2C and Fast-Mode-plus (1 MHz clock) = I 2C 2. Supports the =E2=80=98fairness=E2=80=99 arbitration protocol defined by = the MCTP SMBus/I2C Transport Binding Specification v1.0.0 3. 32KB packets : this is an I2C spec limitation. The HW has no limit on packets size. It has a 16 bytes FIFO which can be reloaded over and over. 4. w\o size byte (for SMB block protocol). 5. Both master and slave. It can also replace modes in run time (requirement for IPMB and MCTP). 6. Bus timing is selected to support both specs. Originally the HW spec stated SMB everywhere . Should I rename the SMB to I2C all over the driver? Thanks, Tali Perry On Mon, Nov 25, 2019 at 5:16 PM Wolfram Sang wrote: > On Thu, Nov 21, 2019 at 11:53:50AM +0200, Tali Perry wrote: > > Add Nuvoton NPCM BMC i2c controller driver. > > > > Signed-off-by: Tali Perry > > Looking at all this SMB_* naming of the registers and also the quirks, > this looks more like an SMBUS controller to me? > > > + // currently I2C slave IF only supports single byte operations. > > + // in order to utilyze the npcm HW FIFO, the driver will ask for > 16bytes > > + // at a time, pack them in buffer, and then transmit them all > together > > + // to the FIFO and onward to the bus . > > + // NACK on read will be once reached to > bus->adap->quirks->max_read_len > > + // sending a NACK whever the backend requests for it is not > supported. > > This for example... > > > +static const struct i2c_adapter_quirks npcm_i2c_quirks =3D { > > + .max_read_len =3D 32768, > > + .max_write_len =3D 32768, > > + .max_num_msgs =3D 2, > > + .flags =3D I2C_AQ_COMB_WRITE_THEN_READ > > +}; > > ... and this. Like SMBus with the only exception of being able to send > 32K in a row. Or? > > --0000000000008c10cc05983a2deb Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
<= font face=3D"monospace">Hi Wolfram,

Thanks for your comments.
The NPCM7XX BMC I2C\SMB controller HW module supports both SMB and I2C= .=C2=A0
It's main features are:
1.=C2=A0Supports Fast-Mode (400 KHz clock) I2C and Fast-Mode-plus (1 MHz clock) I2C
2.=C2=A0Supports the= =E2=80=98fairness=E2=80=99 arbitration protocol defined by the MCTP SMBus/= I2C Transport Binding Specification v1.0.0
3. 32KB packets : this = is an I2C spec limitation. The HW has no limit on packets size. It has a 16= bytes FIFO which can be reloaded over and over.
4. w\o size byte (for SM= B block protocol).
5. Both master and slave. It can also replace modes in= run time (requirement for IPMB and MCTP).
6. Bus timing is selected to s= upport both specs.

Originally the HW spec stated SMB everywhere .= =C2=A0

Should I rename the SMB to I2C all over the driver?<= /div>

<= /font>
Thanks,
Tali Perry


On Mon, Nov 25, 2019 at 5:16 PM Wo= lfram Sang <wsa@the-dreams.de&g= t; wrote:
On Thu= , Nov 21, 2019 at 11:53:50AM +0200, Tali Perry wrote:
> Add Nuvoton NPCM BMC i2c controller driver.
>
> Signed-off-by: Tali Perry <tali.perry1@gmail.com>

Looking at all this SMB_* naming of the registers and also the quirks,
this looks more like an SMBUS controller to me?

> +=C2=A0 =C2=A0 =C2=A0// currently I2C slave IF only supports single by= te operations.
> +=C2=A0 =C2=A0 =C2=A0// in order to utilyze the npcm HW FIFO, the driv= er will ask for 16bytes
> +=C2=A0 =C2=A0 =C2=A0// at a time, pack them in buffer, and then trans= mit them all together
> +=C2=A0 =C2=A0 =C2=A0// to the FIFO and onward to the bus .
> +=C2=A0 =C2=A0 =C2=A0// NACK on read will be once reached to bus->a= dap->quirks->max_read_len
> +=C2=A0 =C2=A0 =C2=A0// sending a NACK whever the backend requests for= it is not supported.

This for example...

> +static const struct i2c_adapter_quirks npcm_i2c_quirks =3D {
> +=C2=A0 =C2=A0 =C2=A0.max_read_len =3D 32768,
> +=C2=A0 =C2=A0 =C2=A0.max_write_len =3D 32768,
> +=C2=A0 =C2=A0 =C2=A0.max_num_msgs =3D 2,
> +=C2=A0 =C2=A0 =C2=A0.flags =3D I2C_AQ_COMB_WRITE_THEN_READ
> +};

... and this. Like SMBus with the only exception of being able to send
32K in a row. Or?

--0000000000008c10cc05983a2deb--