From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-20.3 required=3.0 tests=BAYES_00,DKIMWL_WL_MED, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, HTML_MESSAGE,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_IN_DEF_DKIM_WL autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2E97C4707F for ; Thu, 27 May 2021 03:15:21 +0000 (UTC) Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1B52661358 for ; Thu, 27 May 2021 03:15:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1B52661358 Authentication-Results: mail.kernel.org; dmarc=fail (p=reject dis=none) header.from=google.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4FrCcR5lgBz3004 for ; Thu, 27 May 2021 13:15:19 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=fUiFAf1v; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=google.com (client-ip=2607:f8b0:4864:20::329; helo=mail-ot1-x329.google.com; envelope-from=wltu@google.com; receiver=) Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=google.com header.i=@google.com header.a=rsa-sha256 header.s=20161025 header.b=fUiFAf1v; dkim-atps=neutral Received: from mail-ot1-x329.google.com (mail-ot1-x329.google.com [IPv6:2607:f8b0:4864:20::329]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4FrCbr2Gmtz2xv8 for ; Thu, 27 May 2021 13:14:45 +1000 (AEST) Received: by mail-ot1-x329.google.com with SMTP id i12-20020a05683033ecb02903346fa0f74dso3083300otu.10 for ; Wed, 26 May 2021 20:14:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9JP1GbR3rEx/dCbJid3KvIT4o/F/4RY1pLrN+bpnLP8=; b=fUiFAf1vfVuGH7Vq5iffIYISvx/gy2fbMmdT1DjZ5ZsveSv4SxoQHX2/7YicmdBdC1 7nqaZSfcRIz0t0HzZL9ZfaZWdowSBTR+mNaQzUdlbB6fOvDHPOdSm0CEto0qIpnXaLLA bGok35hzeT3qnUJelPfwVAs6hkDSiKo3QlnFZJzewGUf1tPHU16hyD1O45UgCkPDSpak 2S6hY8BKZ1P5spQwG1Y1Ft/umtkV4qz774kjofLpdLtJ+dFt1DyBMcmrlldI7rd+FCRv 7r89eH45SvwhQc8z2Wj+oJTIusZJ9tmQhuvf5ZDzJ7Rn8oBUIDki0q2CU/08PvcET+o1 pPYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9JP1GbR3rEx/dCbJid3KvIT4o/F/4RY1pLrN+bpnLP8=; b=K9tz12xrwTMZrRdMlMWVizLzh9bEen3NqNVhYEDIb7WuB+zc5tEii4K5DdUC5dY/xF 9iRbNs9WDyZs4JFAtakVg3pxht4zQUApjQ5fiCvdX7ztDbqamUOHg4AWDL+O0+EYxKDb Gbke+dq5+rVgBQeCgChD51G4O7qoLy9FJrV4SLiVbjaXD9HdZSts5DHgGYx1KMPdhQze EONy+YSYGmX8tDUhSPbYki4FkZzTcpz2rWMAHqlwHQq5q4WDyn1HMXVnEY5++NV7Aip9 woCo4gKJg0crJdfXAjXWPzkV0Qk541L0suuGsBRmAbNvIxZyYZ2Gom1dMQamr0utAJ76 UpWg== X-Gm-Message-State: AOAM533Xrdsi7dTiRpIybBIxVrRUA93/PEduzyTe6J9y/58KBE8zgDPQ RNMf0lRrdD79vIUMF7NVgL9EjKPoYirK+hhsORD8/g== X-Google-Smtp-Source: ABdhPJxzZfhiog7xigjdSkdyh/ARNVn5SMx4NUjM4i3kUnLmHdre1CiMyvnusILfTrEgvrwH6nociM6zWUEC/CAGJ68= X-Received: by 2002:a9d:2ee:: with SMTP id 101mr1167210otl.76.1622085281314; Wed, 26 May 2021 20:14:41 -0700 (PDT) MIME-Version: 1.0 References: <20210413161150.2815450-1-wltu@google.com> In-Reply-To: From: Willy Tu Date: Wed, 26 May 2021 20:14:30 -0700 Message-ID: Subject: Re: [PATCH] board: ast2400: Enable SGPIO in SCU To: Joel Stanley Content-Type: multipart/alternative; boundary="000000000000fd5e1c05c3472807" X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: OpenBMC Maillist , Benjamin Fair Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" --000000000000fd5e1c05c3472807 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Wed, May 26, 2021 at 6:57 PM Joel Stanley wrote: > On Wed, 14 Apr 2021 at 00:06, Willy Tu wrote: > > > > Hi Joel, > > > > thanks for the response. > > > > Sorry, I did not update the patch to include the branch name. I'll be > more careful next time. > > > > This change should be in `v2019.04-aspeed-openbmc` and the other patch > in > https://lore.kernel.org/openbmc/20210413161238.2816187-1-wltu@google.com/ > should be in `v2016.07-aspeed-openbmc`. > > Okay. > > > I have not tested this change, but have tested > https://lore.kernel.org/openbmc/20210413161238.2816187-1-wltu@google.com/ > that I based off of (Which I have tested with my setup). Will that be an > issue? > > What branch are you using for your system? > > I strongly encourage you to use the 2019.04 branch if at all possible. > > Some review below. > The system that I was using was based on v2016.07-aspeed-openbmc . It is an old system and we don't plan on migrating the u-boot version for it. We don't have any system that is using aspeed other than this one. > > > On Tue, Apr 13, 2021 at 4:32 PM Joel Stanley wrote: > >> > >> Hi Willy, > >> > >> On Tue, 13 Apr 2021 at 16:11, Willy Tu wrote: > >> > > >> > Add option to enable register for SGPIO in SCU. > >> > > >> > Included new function register values for ast2400 > >> > SCU and enable the SGPIO function in board init. > >> > >> Which branch would you like this patch applied to? > >> > >> > > >> > Signed-off-by: Willy Tu > >> > --- > >> > arch/arm/include/asm/arch-aspeed/scu_ast2400.h | 4 ++++ > >> > arch/arm/mach-aspeed/ast2400/Kconfig | 4 ++++ > >> > arch/arm/mach-aspeed/ast2400/board_common.c | 15 +++++++++++++++ > >> > 3 files changed, 23 insertions(+) > >> > > >> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h > b/arch/arm/include/asm/arch-aspeed/scu_ast2400.h > >> > index 9c5d96ae84..17eaaf3e9d 100644 > >> > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h > >> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2400.h > >> > @@ -75,6 +75,10 @@ > >> > #define SCU_PIN_FUN_SCL2 (1 << 14) > >> > #define SCU_PIN_FUN_SDA1 (1 << 13) > >> > #define SCU_PIN_FUN_SDA2 (1 << 15) > >> > +#define SCU_PIN_FUN_SGPMCK (0x1 << 8) > >> > +#define SCU_PIN_FUN_SGPMLD (0x1 << 9) > >> > +#define SCU_PIN_FUN_SGPMO (0x1 << 10) > >> > +#define SCU_PIN_FUN_SGPMI (0x1 << 11) > >> > > >> > #define SCU_D2PLL_EXT1_OFF (1 << 0) > >> > #define SCU_D2PLL_EXT1_BYPASS (1 << 1) > >> > diff --git a/arch/arm/mach-aspeed/ast2400/Kconfig > b/arch/arm/mach-aspeed/ast2400/Kconfig > >> > index f76276860c..c4e88b5140 100644 > >> > --- a/arch/arm/mach-aspeed/ast2400/Kconfig > >> > +++ b/arch/arm/mach-aspeed/ast2400/Kconfig > >> > @@ -17,6 +17,10 @@ config TARGET_EVB_AST2400 > >> > 20 pin JTAG, pinouts for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs. > >> > endchoice > >> > > >> > +config ENABLE_SGPIO > >> > + tristate "Enable SGPIO in SCU" > >> > + default n > > Note that this is the default default in kconfig, you only need to > specify a default if you want some other behaviour. > > >> > @@ -14,6 +14,21 @@ __weak int board_init(void) > >> > { > >> > gd->bd->bi_boot_params =3D CONFIG_SYS_SDRAM_BASE + 0x100; > >> > > >> > +#ifdef CONFIG_ENABLE_SGPIO > >> > +#define SCU_BASE 0x1e6e2000 > >> > +#define SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control#2*/ > >> > + /* Unlock SCU */ > >> > + writel(SCU_UNLOCK_VALUE, SCU_BASE); > >> > + > >> > + /* Enable SGPIO Master */ > >> > + u32 reg =3D readl(SCU_BASE + SCU_FUN_PIN_CTRL2); > >> > + > >> > + reg |=3D (SCU_PIN_FUN_SGPMI | > >> > + SCU_PIN_FUN_SGPMO | > >> > + SCU_PIN_FUN_SGPMLD | > >> > + SCU_PIN_FUN_SGPMCK); > >> > + writel(reg, SCU_BASE + SCU_FUN_PIN_CTRL2); > >> > +#endif > > Here's what I saw when attempting to compile test your patch: > > In file included from ../arch/arm/mach-aspeed/ast2400/board_common.c:6: > ../arch/arm/mach-aspeed/ast2400/board_common.c: In function =E2=80=98boar= d_init=E2=80=99: > ../arch/arm/mach-aspeed/ast2400/board_common.c:21:16: error: > =E2=80=98SCU_UNLOCK_VALUE=E2=80=99 undeclared (first use in this function= ) > 21 | writel(SCU_UNLOCK_VALUE, SCU_BASE); > | ^~~~~~~~~~~~~~~~ > ../arch/arm/include/asm/io.h:117:38: note: in definition of macro =E2=80= =98writel=E2=80=99 > 117 | #define writel(v,c) ({ u32 __v =3D v; __iowmb(); > __arch_putl(__v,c); __v; }) > | ^ > ../arch/arm/mach-aspeed/ast2400/board_common.c:21:16: note: each > undeclared identifier is reported only once for each function it > appears in > 21 | writel(SCU_UNLOCK_VALUE, SCU_BASE); > | ^~~~~~~~~~~~~~~~ > ../arch/arm/include/asm/io.h:117:38: note: in definition of macro =E2=80= =98writel=E2=80=99 > 117 | #define writel(v,c) ({ u32 __v =3D v; __iowmb(); > __arch_putl(__v,c); __v; }) > | ^ > ../arch/arm/mach-aspeed/ast2400/board_common.c:26:17: error: > =E2=80=98SCU_PIN_FUN_SGPMI=E2=80=99 undeclared (first use in this functio= n) > 26 | reg |=3D (SCU_PIN_FUN_SGPMI | > | ^~~~~~~~~~~~~~~~~ > ../arch/arm/mach-aspeed/ast2400/board_common.c:27:25: error: > =E2=80=98SCU_PIN_FUN_SGPMO=E2=80=99 undeclared (first use in this functio= n) > 27 | SCU_PIN_FUN_SGPMO | > | ^~~~~~~~~~~~~~~~~ > ../arch/arm/mach-aspeed/ast2400/board_common.c:28:25: error: > =E2=80=98SCU_PIN_FUN_SGPMLD=E2=80=99 undeclared (first use in this functi= on) > 28 | SCU_PIN_FUN_SGPMLD | > | ^~~~~~~~~~~~~~~~~~ > ../arch/arm/mach-aspeed/ast2400/board_common.c:29:25: error: > =E2=80=98SCU_PIN_FUN_SGPMCK=E2=80=99 undeclared (first use in this functi= on) > 29 | SCU_PIN_FUN_SGPMCK); > | ^~~~~~~~~~~~~~~~~~ > > > >> > return 0; > >> > } > >> > > >> > -- > >> > 2.31.1.295.g9ea45b61b8-goog > >> > > Thanks for the feedback. I'll address the issue and apply a new patch. Willy Tu --000000000000fd5e1c05c3472807 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
On Wed, May 26, 2021 at 6:57 PM Joel Stan= ley <joel@jms.id.au> wrote:
=
On Wed, 14 Apr 2021 at 00:06, Willy Tu <wltu@google.com> wrote:
>
> Hi Joel,
>
> thanks for the response.
>
> Sorry, I did not update the patch to include the branch name. I'll= be more careful next time.
>
> This change should be in `v2019.04-aspeed-openbmc` and the other patch= in https://lore.kernel.org= /openbmc/20210413161238.2816187-1-wltu@google.com/ should be in `v2016.= 07-aspeed-openbmc`.

Okay.

> I have not tested this change, but have tested=C2=A0 https://lore.kernel.org/openbmc/202104131612= 38.2816187-1-wltu@google.com/ that I based off of (Which I have tested = with my setup). Will that be an issue?

What branch are you using for your system?

I strongly encourage you to use the 2019.04 branch if at all possible.

Some review below.

The system that I wa= s using was based on v2016.07-aspeed-openbmc . It is an old system and we d= on't plan on migrating the u-boot version for it. We don't have any= system that is using aspeed other than this one.
=C2=A0

> On Tue, Apr 13, 2021 at 4:32 PM Joel Stanley <joel@jms.id.au> wrote:
>>
>> Hi Willy,
>>
>> On Tue, 13 Apr 2021 at 16:11, Willy Tu <wltu@google.com> wrote:
>> >
>> > Add option to enable register for SGPIO in SCU.
>> >
>> > Included new function register values for ast2400
>> > SCU and enable the SGPIO function in board init.
>>
>> Which branch would you like this patch applied to?
>>
>> >
>> > Signed-off-by: Willy Tu <wltu@google.com>
>> > ---
>> >=C2=A0 arch/arm/include/asm/arch-aspeed/scu_ast2400.h |=C2=A0 = 4 ++++
>> >=C2=A0 arch/arm/mach-aspeed/ast2400/Kconfig=C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0|=C2=A0 4 ++++
>> >=C2=A0 arch/arm/mach-aspeed/ast2400/board_common.c=C2=A0 =C2= =A0 | 15 +++++++++++++++
>> >=C2=A0 3 files changed, 23 insertions(+)
>> >
>> > diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h b= /arch/arm/include/asm/arch-aspeed/scu_ast2400.h
>> > index 9c5d96ae84..17eaaf3e9d 100644
>> > --- a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h
>> > +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2400.h
>> > @@ -75,6 +75,10 @@
>> >=C2=A0 #define SCU_PIN_FUN_SCL2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0(1 << 14)
>> >=C2=A0 #define SCU_PIN_FUN_SDA1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0(1 << 13)
>> >=C2=A0 #define SCU_PIN_FUN_SDA2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0(1 << 15)
>> > +#define SCU_PIN_FUN_SGPMCK=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0(0x1 << 8)
>> > +#define SCU_PIN_FUN_SGPMLD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0(0x1 << 9)
>> > +#define SCU_PIN_FUN_SGPMO=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 (0x1 << 10)
>> > +#define SCU_PIN_FUN_SGPMI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 (0x1 << 11)
>> >
>> >=C2=A0 #define SCU_D2PLL_EXT1_OFF=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0(1 << 0)
>> >=C2=A0 #define SCU_D2PLL_EXT1_BYPASS=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 (1 << 1)
>> > diff --git a/arch/arm/mach-aspeed/ast2400/Kconfig b/arch/arm/= mach-aspeed/ast2400/Kconfig
>> > index f76276860c..c4e88b5140 100644
>> > --- a/arch/arm/mach-aspeed/ast2400/Kconfig
>> > +++ b/arch/arm/mach-aspeed/ast2400/Kconfig
>> > @@ -17,6 +17,10 @@ config TARGET_EVB_AST2400
>> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A020 pin JTAG, pinouts = for 14 I2Cs, 3 SPIs and eSPI, 8 PWMs.
>> >=C2=A0 endchoice
>> >
>> > +config ENABLE_SGPIO
>> > +=C2=A0 =C2=A0 tristate "Enable SGPIO in SCU"
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0default n

Note that this is the default default in kconfig, you only need to
specify a default if you want some other behaviour.

>> > @@ -14,6 +14,21 @@ __weak int board_init(void)
>> >=C2=A0 {
>> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gd->bd->bi_boot_params= =3D CONFIG_SYS_SDRAM_BASE + 0x100;
>> >
>> > +#ifdef CONFIG_ENABLE_SGPIO
>> > +#define SCU_BASE 0x1e6e2000
>> > +#define SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control= #2*/
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Unlock SCU */
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0writel(SCU_UNLOCK_VALUE, SCU_BASE= );
>> > +
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Enable SGPIO Master */
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 reg =3D readl(SCU_BASE + SCU_= FUN_PIN_CTRL2);
>> > +
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0reg |=3D (SCU_PIN_FUN_SGPMI=C2=A0= |
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMO=C2=A0 |
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMLD |
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMCK);
>> > +=C2=A0 =C2=A0 =C2=A0 =C2=A0writel(reg, SCU_BASE + SCU_FUN_PI= N_CTRL2);
>> > +#endif

Here's what I saw when attempting to compile test your patch:

In file included from ../arch/arm/mach-aspeed/ast2400/board_common.c:6:
../arch/arm/mach-aspeed/ast2400/board_common.c: In function =E2=80=98board_= init=E2=80=99:
../arch/arm/mach-aspeed/ast2400/board_common.c:21:16: error:
=E2=80=98SCU_UNLOCK_VALUE=E2=80=99 undeclared (first use in this function)<= br> =C2=A0 =C2=A021 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(SCU_UNLOCK_VALUE,= SCU_BASE);
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 ^~~~~~~~~~~~~~~~
../arch/arm/include/asm/io.h:117:38: note: in definition of macro =E2=80=98= writel=E2=80=99
=C2=A0 117 | #define writel(v,c)=C2=A0 =C2=A0 =C2=A0({ u32 __v =3D v; __iow= mb();
__arch_putl(__v,c); __v; })
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 ^
../arch/arm/mach-aspeed/ast2400/board_common.c:21:16: note: each
undeclared identifier is reported only once for each function it
appears in
=C2=A0 =C2=A021 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0writel(SCU_UNLOCK_VALUE,= SCU_BASE);
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 ^~~~~~~~~~~~~~~~
../arch/arm/include/asm/io.h:117:38: note: in definition of macro =E2=80=98= writel=E2=80=99
=C2=A0 117 | #define writel(v,c)=C2=A0 =C2=A0 =C2=A0({ u32 __v =3D v; __iow= mb();
__arch_putl(__v,c); __v; })
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 ^
../arch/arm/mach-aspeed/ast2400/board_common.c:26:17: error:
=E2=80=98SCU_PIN_FUN_SGPMI=E2=80=99 undeclared (first use in this function)=
=C2=A0 =C2=A026 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0reg |=3D (SCU_PIN_FUN_SG= PMI=C2=A0 |
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0^~~~~~~~~~~~~~~~~
../arch/arm/mach-aspeed/ast2400/board_common.c:27:25: error:
=E2=80=98SCU_PIN_FUN_SGPMO=E2=80=99 undeclared (first use in this function)=
=C2=A0 =C2=A027 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMO=C2=A0 |
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0^~~~~~~~~~~~~~~~~
../arch/arm/mach-aspeed/ast2400/board_common.c:28:25: error:
=E2=80=98SCU_PIN_FUN_SGPMLD=E2=80=99 undeclared (first use in this function= )
=C2=A0 =C2=A028 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMLD |
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0^~~~~~~~~~~~~~~~~~
../arch/arm/mach-aspeed/ast2400/board_common.c:29:25: error:
=E2=80=98SCU_PIN_FUN_SGPMCK=E2=80=99 undeclared (first use in this function= )
=C2=A0 =C2=A029 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SCU_PIN_FUN_SGPMCK);
=C2=A0 =C2=A0 =C2=A0 |=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0^~~~~~~~~~~~~~~~~~


>> >=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
>> >=C2=A0 }
>> >
>> > --
>> > 2.31.1.295.g9ea45b61b8-goog
>> >

Thanks for the feedback. = I'll address the issue and apply a new patch.

= Willy Tu
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