On Tue, Apr 13, 2021 at 5:06 PM Willy Tu <wltu@google.com> wrote:

Hi Joel,

thanks for the response.

Sorry, I did not u= pdate the patch to include the branch name. I'll be more careful next t= ime.

This change should be in `v2019.04-aspeed= -openbmc` and the other patch in=C2=A0https://= lore.kernel.org/openbmc/20210413161238.2816187-1-wltu@google.com/=C2=A0= should be in `v2016.07-aspeed-openbmc`.

I have not= tested this change, but have tested=C2=A0=C2=A0https://lore.kernel.org/openbmc/20210413161238.2816187-1-wltu@google.com/= =C2=A0that I based off of (Which I have tested with my setup). Will tha= t be an issue?

Best,

Will= y Tu

On Tue, Apr 13, 2021 at 4:32 PM Joel Stanley <joel@jms.id.au> wrote:
=

Hi Willy,

On Tue, 13 Apr 2021 at 16:11, Willy Tu <wltu@google.com> wrote:
>
> Add option to enable register for SGPIO in SCU.
>
> Included new function register values for ast2400
> SCU and enable the SGPIO function in board init.

Which branch would you like this patch applied to?

>
> Signed-off-by: Willy Tu <wltu@google.com>
> ---
>=C2=A0 arch/arm/include/asm/arch-aspeed/scu_ast2400.h |=C2=A0 4 ++++ >=C2=A0 arch/arm/mach-aspeed/ast2400/Kconfig=C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0|=C2=A0 4 ++++
>=C2=A0 arch/arm/mach-aspeed/ast2400/board_common.c=C2=A0 =C2=A0 | 15 ++= +++++++++++++
>=C2=A0 3 files changed, 23 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h b/arch/arm= /include/asm/arch-aspeed/scu_ast2400.h
> index 9c5d96ae84..17eaaf3e9d 100644
> --- a/arch/arm/include/asm/arch-aspeed/scu_ast2400.h
> +++ b/arch/arm/include/asm/arch-aspeed/scu_ast2400.h
> @@ -75,6 +75,10 @@
>=C2=A0 #define SCU_PIN_FUN_SCL2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(1 << 14)
>=C2=A0 #define SCU_PIN_FUN_SDA1=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(1 << 13)
>=C2=A0 #define SCU_PIN_FUN_SDA2=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0(1 << 15)
> +#define SCU_PIN_FUN_SGPMCK=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(0x1 << 8)
> +#define SCU_PIN_FUN_SGPMLD=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0(0x1 << 9)
> +#define SCU_PIN_FUN_SGPMO=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 (0x1 << 10)
> +#define SCU_PIN_FUN_SGPMI=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 (0x1 << 11)
>
>=C2=A0 #define SCU_D2PLL_EXT1_OFF=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0(1 << 0)
>=C2=A0 #define SCU_D2PLL_EXT1_BYPASS=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = (1 << 1)
> diff --git a/arch/arm/mach-aspeed/ast2400/Kconfig b/arch/arm/mach-aspe= ed/ast2400/Kconfig
> index f76276860c..c4e88b5140 100644
> --- a/arch/arm/mach-aspeed/ast2400/Kconfig
> +++ b/arch/arm/mach-aspeed/ast2400/Kconfig
> @@ -17,6 +17,10 @@ config TARGET_EVB_AST2400
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A020 pin JTAG, pinouts for 14 I2= Cs, 3 SPIs and eSPI, 8 PWMs.
>=C2=A0 endchoice
>
> +config ENABLE_SGPIO
> +=C2=A0 =C2=A0 tristate "Enable SGPIO in SCU"
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0default n
> +
>=C2=A0 source "board/aspeed/evb_ast2400/Kconfig"
>
>=C2=A0 endif
> diff --git a/arch/arm/mach-aspeed/ast2400/board_common.c b/arch/arm/ma= ch-aspeed/ast2400/board_common.c
> index 3829b06934..eca2ef03e5 100644
> --- a/arch/arm/mach-aspeed/ast2400/board_common.c
> +++ b/arch/arm/mach-aspeed/ast2400/board_common.c
> @@ -14,6 +14,21 @@ __weak int board_init(void)
>=C2=A0 {
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0gd->bd->bi_boot_params =3D CONF= IG_SYS_SDRAM_BASE + 0x100;
>
> +#ifdef CONFIG_ENABLE_SGPIO
> +#define SCU_BASE 0x1e6e2000
> +#define SCU_FUN_PIN_CTRL2 0x84 /* Multi-function Pin Control#2*/
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Unlock SCU */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0writel(SCU_UNLOCK_VALUE, SCU_BASE);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0/* Enable SGPIO Master */
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0u32 reg =3D readl(SCU_BASE + SCU_FUN_PIN_C= TRL2);
> +
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0reg |=3D (SCU_PIN_FUN_SGPMI=C2=A0 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0SCU_PIN_FUN_SGPMO=C2=A0 |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0SCU_PIN_FUN_SGPMLD |
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0SCU_PIN_FUN_SGPMCK);
> +=C2=A0 =C2=A0 =C2=A0 =C2=A0writel(reg, SCU_BASE + SCU_FUN_PIN_CTRL2);=
> +#endif
>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0return 0;
>=C2=A0 }
>
> --
> 2.31.1.295.g9ea45b61b8-goog
>