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From: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
To: Andrew Jeffery <andrew@aj.id.au>, Rob Herring <robh+dt@kernel.org>, Joel
 Stanley <joel@jms.id.au>, Michael Turquette <mturquette@baylibre.com>,
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 "openbmc@lists.ozlabs.org" <openbmc@lists.ozlabs.org>, linux-mmc
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Subject: RE: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
Thread-Topic: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD device
Thread-Index: AQHXygJu7aSIKaH77U+Hz3adbFpzOav2SKZQ
Date: Sat, 6 Nov 2021 10:01:35 +0000
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References: <20210922103116.30652-1-chin-ting_kuo@aspeedtech.com>
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> -----Original Message-----
> From: Andrew Jeffery <andrew@aj.id.au>
> Sent: Tuesday, October 26, 2021 8:43 AM
> Subject: Re: [PATCH 03/10] dts: aspeed: ast2600: Support SDR50 for SD dev=
ice
>=20
>=20
>=20
> On Wed, 22 Sep 2021, at 20:01, Chin-Ting Kuo wrote:
> > The maximum frequency for SD controller on AST2600 EVB is 100MHz. In
> > order to achieve 100MHz, sd-uhs-sdr50 property should be added and the
> > driver will set the SDR50 supported bit in capability 2 register
> > during probing stage.
> >
> > Signed-off-by: Chin-Ting Kuo <chin-ting_kuo@aspeedtech.com>
>=20
> As this is a limitation of the SoC it should be done in aspeed-g6.dtsi.
> Unless I've misunderstood?
>=20

Okay, it will be updated in the next patch version.

> Andrew
>=20
> > ---
> >  arch/arm/boot/dts/aspeed-ast2600-evb.dts | 2 ++
> >  1 file changed, 2 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > index b7eb552640cb..4551dba499c2 100644
> > --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts
> > @@ -280,6 +280,7 @@
> >  &sdhci0 {
> >  	status =3D "okay";
> >  	bus-width =3D <4>;
> > +	sd-uhs-sdr50;
> >  	max-frequency =3D <100000000>;
> >  	sdhci-drive-type =3D /bits/ 8 <3>;
> >  	sdhci-caps-mask =3D <0x7 0x0>;
> > @@ -292,6 +293,7 @@
> >  &sdhci1 {
> >  	status =3D "okay";
> >  	bus-width =3D <4>;
> > +	sd-uhs-sdr50;
> >  	max-frequency =3D <100000000>;
> >  	sdhci-drive-type =3D /bits/ 8 <3>;
> >  	sdhci-caps-mask =3D <0x7 0x0>;
> > --
> > 2.17.1

Chin-Ting