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Received: by mail.messagingengine.com (Postfix) with ESMTPA; Wed, 9 Feb 2022 14:56:26 -0500 (EST) Date: Wed, 9 Feb 2022 13:56:24 -0600 From: Patrick Williams To: Michael Shen Subject: Re: Propose a new application for reading DIMM SPD directly Message-ID: References:

MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="2L5QQTfvtP0WgKxQ" Content-Disposition: inline In-Reply-To: X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org, Benjamin Fair Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" --2L5QQTfvtP0WgKxQ Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Feb 08, 2022 at 04:23:12PM +0800, Michael Shen wrote: > On Tue, Feb 8, 2022 at 3:11 PM Patrick Williams wrote: > > On Tue, Feb 08, 2022 at 01:10:37PM +0800, Michael Shen wrote: > > > If I understand correctly, the main method for obtaining the SPD > > > information in openbmc is from SMBIOS which is prepared by BIOS. And > > > We are exploring another way that excludes the involvement of BIOS. > > > > Unless you're proposing that the BIOS itself comes to the BMC to get th= e SPD > > data, I'm somewhat surprised you could come up with a hardware design t= o make > > this work. Due to the number of DIMM channels and the limited number o= f CS pins > > on JEDEC DIMMs, you're going to have muxes on the bus somewhere. Mixin= g muxes > > and multi-master access is pretty problematic. >=20 > Yes, we need an additional MUX for switching the master(between BIOS or B= MC). > However, compared to the single-master(BIOS only) design, this MUX is > the only hardware difference. >=20 > > Either the BIOS and BMC are > > fighting over the mux, which is going to mess with the mux driver's vie= w of the > > world, or you've got one mux for each in which case you're switching ma= sters > > onto a bus, which violates a few i2c design rules. >=20 > BIOS owns the MUX select pin and it can decide who owns the SPD(I2C/I3C) = bus. > From my understanding, BIOS only needs to read SPD during the POST stage. > For the rest of time, BIOS will hand over the SPD bus to BMC. That seems like it might work. You'll have to deal with the time when the = BIOS has the mux in the BMC code somehow. Ideally I'd ask for the mux select to= also be fed to the BMC as an input GPIO so that you can differentiate between "we don't own the mux" and "all the devices are NAKing us". > > You should take a look at what is already existing in fru-device (part = of > > entity-manager repository). This is already doing this for IPMI-format= EEPROM > > data. We should be able to replicate/enhance this code, in the same re= pository, > > to handle SPD format. >=20 > I am not sure if it's a good idea to put it into the entity-manager > repo. As you said EM > is designed for IPMI-format EEPROM. Adding another parser into that > repo may violate > EM's design. I'm not sure why it would be an issue. Hopefully one of the maintainers of= that repo can weigh in. I wouldn't expect "parsing only IPMI-format EEPROMs" is= a design but just the current state of implementation. --=20 Patrick Williams --2L5QQTfvtP0WgKxQ Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEBGD9ii4LE9cNbqJBqwNHzC0AwRkFAmIEHGUACgkQqwNHzC0A wRk2Hw//UqGpzxlPrwvuEZ7dNJwu25syCoQEYbxizabELa1zG4JzZcwwW0Cm6Qkq sDpZZN6z4wqjqN5EmqjWZF1347Q0RRR/i8GNJozOnl84NGyTANvrHQs5yIbji2hj xp5vfABxK1EfDAvpkdSSYkjDAS++rinlCAGog6XLD1gQKWNHWwvFZZKpuYrEuakj n2bEnabNRZBsub3rrJgZcK+UXfRETqGkQAynSVv1t76Um9R+nlMCpuUA8besbsp3 M9lJu+GLg24JkqjJt2+ELMftT4kS091HFAOKEjZ1S0DMSa0xmY3ekEfQLA1tRNEp p38cP76B9RVwUg61UdXboRYYu2iZjPMoP+bGHv71J9yDkO4vyne/2Oh0ZQ2Sl4dS lLju+yb64KS9a9IYNb39HW+blXb0aK2O46V9tKFa9KwyA2Z4h/QMUjF1Yk4BYmvK 0omVF+b6Pgu4yEP4YcQgyT8Se6FDSqEujHAECFRuh37TCEfWl5HmGVOq1C27+57m +f3XyawKQXyHh2Het8CxWNpSXCSjPY+Ta6KbiCSEH5Uth6PwkECVdXE/sYtuzA53 7cowVku7zEpKd1eTOayokNaWwuSJ7bPQwcg3WQrtURVwXnYkEi7dM+3dQyGjvjLC /NVzgxQ+CRI6YxMK2gx7AXGg6R4Pd6iJoKEhFFgfEQ1IAwAjl0k= =kznT -----END PGP SIGNATURE----- --2L5QQTfvtP0WgKxQ--