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([2600:1700:e321:62f0:329c:23ff:fee3:9d7c]) by smtp.gmail.com with ESMTPSA id s41-20020a05683043a900b005ad2328c137sm3147167otv.46.2022.02.26.15.54.43 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 26 Feb 2022 15:54:44 -0800 (PST) Message-ID: Date: Sat, 26 Feb 2022 15:54:42 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.5.0 Content-Language: en-US To: Zev Weiss , linux-hwmon@vger.kernel.org, Jean Delvare References: <20220226133047.6226-1-zev@bewilderbeest.net> From: Guenter Roeck Subject: Re: [PATCH 0/5] hwmon: (nct6775) Add i2c support In-Reply-To: <20220226133047.6226-1-zev@bewilderbeest.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, Rob Herring , linux-kernel@vger.kernel.org, Renze Nicolai Errors-To: openbmc-bounces+openbmc=archiver.kernel.org@lists.ozlabs.org Sender: "openbmc" On 2/26/22 05:30, Zev Weiss wrote: > Hello, > > This patch series augments the existing nct6775 driver with support > for the hardware's i2c interface. > > Thus far the nct6775 driver has only supported the LPC interface, > which is the main interface by which the Super-I/O chip is typically > connected to the host (x86) processor. > > However, these chips also provide an i2c interface, which can provide > a way for a BMC to also monitor sensor readings from them. On some > systems (such as the ASRock Rack ROMED8HM3 and X570-D4U) this may be > the only way for the BMC to monitor host CPU temperatures (e.g. to > indirectly access a TSI interface); this functionality is thus an > important component of enabling OpenBMC to support such systems. > > In such an arrangement the Super-I/O chip is simultaneously controlled > by two independent processors (the host and the BMC) which typically > do not coordinate their accesses with each other. In order to avoid > conflicts between the two, the i2c driver avoids all writes to the > device, since the BMC's needs with the hardware are merely that it be > able to retrieve sensor readings. This allows the host processor to > remain ultimately in control of the chip and unaware of the BMC's use > of it at all. > > The sole exception to the "no writes" rule for the i2c driver is for > the bank-select register -- while I haven't been able to find any > explicit statement in the Nuvoton datasheets guaranteeing this, all > experiments I've done have indicated that, as one might hope, the i2c > interface has its own bank-select register independent of the one used > by the LPC interface. > That will a more detailed confirmation. Please explain in detail the experiments you have done. Other chips (specifically those served by the it87 driver) have the same problem, and there it was never really solved. That resulted in random crashes. I don't want to end up in the same situation. > In terms of code structure, the approach taken in this series is to > split the LPC-specific parts of the driver out into a separate module > (called nct6775-platform), leaving the interface-independent parts in > a generic driver (called nct6775-core). The nct6775-i2c driver is > then added as an additional consumer of the nct6775-core module's > functionality. > How about wmi ? Shouldn't that be separated as well ? Guenter > The first two patches make some relatively small infrastructural > changes to the nct6775 driver; the bulk of the core/platform driver > split is in the third patch. The final two patches add DT bindings > and the i2c driver itself. > > I've tested the nct6775-platform and nct6775-i2c drivers with the > NCT6779D in an ASRock ROMED8HM3 system (the latter driver on its > AST2500 BMC); both seem to work as expected. Broader testing would of > course be welcome though, as is review feedback. >