From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: "Jason A. Donenfeld" <Jason@zx2c4.com>,
Openrisc <openrisc@lists.librecores.org>,
Jia Liu <proljc@gmail.com>
Subject: [PULL 2/4] hw/openrisc: support 4 serial ports in or1ksim
Date: Sun, 15 May 2022 10:39:46 +0900 [thread overview]
Message-ID: <20220515013948.2993495-3-shorne@gmail.com> (raw)
In-Reply-To: <20220515013948.2993495-1-shorne@gmail.com>
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 99b14940f4..6873124f74 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -71,6 +71,10 @@ enum {
OR1KSIM_ETHOC_IRQ = 4,
};
+enum {
+ OR1KSIM_UART_COUNT = 4
+};
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -239,11 +243,13 @@ static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
hwaddr size, int num_cpus,
- OpenRISCCPU *cpus[], int irq_pin)
+ OpenRISCCPU *cpus[], int irq_pin,
+ int uart_idx)
{
void *fdt = state->fdt;
char *nodename;
qemu_irq serial_irq;
+ char alias[sizeof("uart0")];
int i;
if (num_cpus > 1) {
@@ -258,7 +264,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
serial_irq = get_cpu_irq(cpus, 0, irq_pin);
}
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
+ DEVICE_NATIVE_ENDIAN);
/* Add device tree node for serial. */
nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
@@ -271,7 +278,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
/* The /chosen node is created during fdt creation. */
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ snprintf(alias, sizeof(alias), "uart%d", uart_idx);
+ qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
g_free(nodename);
}
@@ -414,9 +422,11 @@ static void openrisc_sim_init(MachineState *machine)
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
- openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base,
- or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus,
- OR1KSIM_UART_IRQ);
+ for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
+ openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
+ or1ksim_memmap[OR1KSIM_UART].size * n,
+ or1ksim_memmap[OR1KSIM_UART].size,
+ smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
load_addr = openrisc_load_kernel(ram_size, kernel_filename);
if (load_addr > 0) {
--
2.31.1
next prev parent reply other threads:[~2022-05-15 1:40 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-15 1:39 [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15 Stafford Horne
2022-05-15 1:39 ` [PULL 1/4] hw/openrisc: page-align FDT address Stafford Horne
2022-05-15 1:39 ` Stafford Horne [this message]
2022-05-15 1:39 ` [PULL 3/4] hw/openrisc: use right OMPIC size variable Stafford Horne
2022-05-15 1:39 ` [PULL 4/4] target/openrisc: Do not reset delay slot flag on early tb exit Stafford Horne
2022-05-15 23:12 ` [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15 Richard Henderson
2022-05-15 23:50 ` Stafford Horne
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