From: Stafford Horne <shorne@gmail.com>
To: QEMU Development <qemu-devel@nongnu.org>
Cc: Linux OpenRISC <linux-openrisc@vger.kernel.org>,
Stafford Horne <shorne@gmail.com>
Subject: [PATCH 2/3] target/openrisc: Set PC to cpu state on FPU exception
Date: Tue, 2 May 2023 19:57:30 +0100 [thread overview]
Message-ID: <20230502185731.3543420-3-shorne@gmail.com> (raw)
In-Reply-To: <20230502185731.3543420-1-shorne@gmail.com>
Store the PC to ensure the correct value can be read in the exception
handler.
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/fpu_helper.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c
index f9e34fa2cc..1feebb9ac7 100644
--- a/target/openrisc/fpu_helper.c
+++ b/target/openrisc/fpu_helper.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "cpu.h"
+#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "exception.h"
#include "fpu/softfloat.h"
@@ -55,6 +56,9 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
if (tmp) {
env->fpcsr |= tmp;
if (env->fpcsr & FPCSR_FPEE) {
+ CPUState *cs = env_cpu(env);
+
+ cpu_restore_state(cs, GETPC());
helper_exception(env, EXCP_FPE);
}
}
--
2.39.1
next prev parent reply other threads:[~2023-05-02 18:57 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-02 18:57 [PATCH 0/3] OpenRISC updates for user space FPU Stafford Horne
2023-05-02 18:57 ` [PATCH 1/3] target/openrisc: Allow fpcsr access in user mode Stafford Horne
2023-05-03 6:29 ` Stafford Horne
2023-05-02 18:57 ` Stafford Horne [this message]
2023-05-03 7:36 ` [PATCH 2/3] target/openrisc: Set PC to cpu state on FPU exception Richard Henderson
2023-05-03 9:12 ` Stafford Horne
2023-05-02 18:57 ` [PATCH 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Stafford Horne
2023-05-03 7:37 ` Richard Henderson
2023-05-03 9:14 ` Stafford Horne
2023-05-03 9:41 ` Richard Henderson
2023-05-03 16:31 ` Stafford Horne
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