[V2,0/2] perf: Add Tremont support
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Message ID 1554922629-126287-1-git-send-email-kan.liang@linux.intel.com
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  • perf: Add Tremont support
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Liang, Kan April 10, 2019, 6:57 p.m. UTC
From: Kan Liang <kan.liang@linux.intel.com>

The patch series intends to add Tremont support for Linux perf.

The patch series is on top of Icelake V5 patch series (with Peter's cleanup patch).
https://lkml.org/lkml/2019/4/8/630

PATCH 1: A fix for Icelake V5 patch series (with Peter's cleanup patch).
         It can be merged back into "Subject: perf/x86/intel: Add Icelake support"
PATCH 2: Tremont core PMU support.

Changes since V1:
- The previous patch "perf/x86/intel: Support adaptive PEBS for fixed counters"
  will be merged back.
- New patch to fix the checking for instruction event.
- Allow instruction:ppp on generic purpose counter 0

Kan Liang (2):
  perf/x86/intel: Fix the checking for instruction event
  perf/x86/intel: Add Tremont core PMU support

 arch/x86/events/intel/core.c | 96 +++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 95 insertions(+), 1 deletion(-)