[00/15] dmaengine: dw-axi-dmac: support Intel KeemBay AxiDMA
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Message ID 20201012042200.29787-1-jee.heng.sia@intel.com
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Sia Jee Heng Oct. 12, 2020, 4:21 a.m. UTC
The below patch series are to support AxiDMA running on Intel KeemBay SoC.
The base driver is dw-axi-dmac but code refactoring is needed, for example:
- Support YAML Schemas DT binding.
- Replacing Linked List with virtual descriptor management.
- Remove unrelated hw desc stuff from dma memory pool.
- Manage dma memory pool alloc/destroy based on channel activity.
- Support dmaengine device_sync() callback.
- Support dmaengine device_config().
- Support dmaegnine device_prep_slave_sg().
- Support dmaengine device_prep_dma_cyclic().
- Support of_dma_controller_register().
- Support burst residue granularity.
- Support Intel KeemBay AxiDMA registers.
- Support Intel KeemBay AxiDMA device handshake.
- Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
- Add constraint to Max segment size.

This patch set is to replace the patch series submitted at:
https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-jee.heng.sia@intel.com/

This patch series are tested on Intel KeemBay platform.


Sia Jee Heng (15):
  dt-bindings: dma: Add YAML schemas for dw-axi-dmac
  dmaengine: dw-axi-dmac: simplify descriptor management
  dmaengine: dw-axi-dmac: move dma_pool_create() to
    alloc_chan_resources()
  dmaengine: dw-axi-dmac: Add device_synchronize() callback
  dmaengine: dw-axi-dmac: Add device_config operation
  dmaengine: dw-axi-dmac: Support device_prep_slave_sg
  dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
  dmaengine: dw-axi-dmac: Support of_dma_controller_register()
  dmaengine: dw-axi-dmac: Support burst residue granularity
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
  dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
  dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
  dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD
    registers
  dmaengine: dw-axi-dmac: Set constraint to the Max segment size

 .../bindings/dma/snps,dw-axi-dmac.txt         |  39 -
 .../bindings/dma/snps,dw-axi-dmac.yaml        | 149 ++++
 .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 696 +++++++++++++++---
 drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  33 +-
 4 files changed, 783 insertions(+), 134 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
 create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml

Comments

Andy Shevchenko Oct. 12, 2020, 1:59 p.m. UTC | #1
On Mon, Oct 12, 2020 at 12:21:45PM +0800, Sia Jee Heng wrote:
> The below patch series are to support AxiDMA running on Intel KeemBay SoC.
> The base driver is dw-axi-dmac but code refactoring is needed, for example:
> - Support YAML Schemas DT binding.
> - Replacing Linked List with virtual descriptor management.
> - Remove unrelated hw desc stuff from dma memory pool.
> - Manage dma memory pool alloc/destroy based on channel activity.
> - Support dmaengine device_sync() callback.
> - Support dmaengine device_config().
> - Support dmaegnine device_prep_slave_sg().
> - Support dmaengine device_prep_dma_cyclic().
> - Support of_dma_controller_register().
> - Support burst residue granularity.
> - Support Intel KeemBay AxiDMA registers.
> - Support Intel KeemBay AxiDMA device handshake.
> - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
> - Add constraint to Max segment size.
> 
> This patch set is to replace the patch series submitted at:
> https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-jee.heng.sia@intel.com/

And it means effectively the bumped version, besides the fact that you double
sent this one...


Please fix and resend. Note, now is merge window is open. Depends on
maintainer's flow it may be good or bad time to resend with properly formed
changelog and version of the series.

> This patch series are tested on Intel KeemBay platform.
> 
> 
> Sia Jee Heng (15):
>   dt-bindings: dma: Add YAML schemas for dw-axi-dmac
>   dmaengine: dw-axi-dmac: simplify descriptor management
>   dmaengine: dw-axi-dmac: move dma_pool_create() to
>     alloc_chan_resources()
>   dmaengine: dw-axi-dmac: Add device_synchronize() callback
>   dmaengine: dw-axi-dmac: Add device_config operation
>   dmaengine: dw-axi-dmac: Support device_prep_slave_sg
>   dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
>   dmaengine: dw-axi-dmac: Support of_dma_controller_register()
>   dmaengine: dw-axi-dmac: Support burst residue granularity
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
>   dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
>   dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD
>     registers
>   dmaengine: dw-axi-dmac: Set constraint to the Max segment size
> 
>  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 -
>  .../bindings/dma/snps,dw-axi-dmac.yaml        | 149 ++++
>  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 696 +++++++++++++++---
>  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  33 +-
>  4 files changed, 783 insertions(+), 134 deletions(-)
>  delete mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
>  create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> 
> -- 
> 2.18.0
>
Sia Jee Heng Oct. 13, 2020, 5:49 a.m. UTC | #2
> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: 12 October 2020 9:59 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: vkoul@kernel.org; Eugeniy.Paltsev@synopsys.com;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> AxiDMA
> 
> On Mon, Oct 12, 2020 at 12:21:45PM +0800, Sia Jee Heng wrote:
> > The below patch series are to support AxiDMA running on Intel KeemBay SoC.
> > The base driver is dw-axi-dmac but code refactoring is needed, for example:
> > - Support YAML Schemas DT binding.
> > - Replacing Linked List with virtual descriptor management.
> > - Remove unrelated hw desc stuff from dma memory pool.
> > - Manage dma memory pool alloc/destroy based on channel activity.
> > - Support dmaengine device_sync() callback.
> > - Support dmaengine device_config().
> > - Support dmaegnine device_prep_slave_sg().
> > - Support dmaengine device_prep_dma_cyclic().
> > - Support of_dma_controller_register().
> > - Support burst residue granularity.
> > - Support Intel KeemBay AxiDMA registers.
> > - Support Intel KeemBay AxiDMA device handshake.
> > - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
> > - Add constraint to Max segment size.
> >
> > This patch set is to replace the patch series submitted at:
> > https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-je
> > e.heng.sia@intel.com/
> 
> And it means effectively the bumped version, besides the fact that you double
> sent this one...
> 
> 
> Please fix and resend. Note, now is merge window is open. Depends on
> maintainer's flow it may be good or bad time to resend with properly formed
> changelog and version of the series.
[>>] Thanks. Will resend the patch set with v1 in the header.
> 
> > This patch series are tested on Intel KeemBay platform.
> >
> >
> > Sia Jee Heng (15):
> >   dt-bindings: dma: Add YAML schemas for dw-axi-dmac
> >   dmaengine: dw-axi-dmac: simplify descriptor management
> >   dmaengine: dw-axi-dmac: move dma_pool_create() to
> >     alloc_chan_resources()
> >   dmaengine: dw-axi-dmac: Add device_synchronize() callback
> >   dmaengine: dw-axi-dmac: Add device_config operation
> >   dmaengine: dw-axi-dmac: Support device_prep_slave_sg
> >   dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
> >   dmaengine: dw-axi-dmac: Support of_dma_controller_register()
> >   dmaengine: dw-axi-dmac: Support burst residue granularity
> >   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
> >   dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
> >   dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
> >   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
> >   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD
> >     registers
> >   dmaengine: dw-axi-dmac: Set constraint to the Max segment size
> >
> >  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 -
> >  .../bindings/dma/snps,dw-axi-dmac.yaml        | 149 ++++
> >  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 696 +++++++++++++++---
> >  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  33 +-
> >  4 files changed, 783 insertions(+), 134 deletions(-)  delete mode
> > 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
> >  create mode 100644
> > Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml
> >
> > --
> > 2.18.0
> >
> 
> --
> With Best Regards,
> Andy Shevchenko
>
Vinod Koul Oct. 13, 2020, 7:01 a.m. UTC | #3
On 13-10-20, 05:49, Sia, Jee Heng wrote:
> > >
> > > This patch set is to replace the patch series submitted at:
> > > https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-je
> > > e.heng.sia@intel.com/
> > 
> > And it means effectively the bumped version, besides the fact that you double
> > sent this one...
> > 
> > 
> > Please fix and resend. Note, now is merge window is open. Depends on
> > maintainer's flow it may be good or bad time to resend with properly formed
> > changelog and version of the series.

yeah sorry I wont look at it till merge window closes

> [>>] Thanks. Will resend the patch set with v1 in the header.

Should this be v1, v1 was the first post, this would be v2!

Please use git format-patch -v2 to autogenerate version headers in
patches..

I thought Intel folks had internal review list to take care of these
things, is it no longer used..?
Sia Jee Heng Oct. 13, 2020, 7:12 a.m. UTC | #4
> -----Original Message-----
> From: Vinod Koul <vkoul@kernel.org>
> Sent: 13 October 2020 3:01 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>;
> Eugeniy.Paltsev@synopsys.com; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: Re: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> AxiDMA
> 
> On 13-10-20, 05:49, Sia, Jee Heng wrote:
> > > >
> > > > This patch set is to replace the patch series submitted at:
> > > > https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-emai
> > > > l-je
> > > > e.heng.sia@intel.com/
> > >
> > > And it means effectively the bumped version, besides the fact that
> > > you double sent this one...
> > >
> > >
> > > Please fix and resend. Note, now is merge window is open. Depends on
> > > maintainer's flow it may be good or bad time to resend with properly
> > > formed changelog and version of the series.
> 
> yeah sorry I wont look at it till merge window closes
[>>] Sorry.
> 
> > [>>] Thanks. Will resend the patch set with v1 in the header.
> 
> Should this be v1, v1 was the first post, this would be v2!
> 
[>>] Thanks for the correction. I meant v2.
> Please use git format-patch -v2 to autogenerate version headers in patches..
> 
> I thought Intel folks had internal review list to take care of these things, is it no
> longer used..?
[>>] We are, but I am confuse on what should I do to the existing patch set sent in 
https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-jee.heng.sia@intel.com/. There is no response from anyone.
> 
> --
> ~Vinod
Vinod Koul Oct. 13, 2020, 7:16 a.m. UTC | #5
On 13-10-20, 07:12, Sia, Jee Heng wrote:
> 
> 
> > -----Original Message-----
> > From: Vinod Koul <vkoul@kernel.org>
> > Sent: 13 October 2020 3:01 PM
> > To: Sia, Jee Heng <jee.heng.sia@intel.com>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>;
> > Eugeniy.Paltsev@synopsys.com; dmaengine@vger.kernel.org; linux-
> > kernel@vger.kernel.org
> > Subject: Re: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> > AxiDMA
> > 
> > On 13-10-20, 05:49, Sia, Jee Heng wrote:
> > > > >
> > > > > This patch set is to replace the patch series submitted at:
> > > > > https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-emai
> > > > > l-je
> > > > > e.heng.sia@intel.com/
> > > >
> > > > And it means effectively the bumped version, besides the fact that
> > > > you double sent this one...
> > > >
> > > >
> > > > Please fix and resend. Note, now is merge window is open. Depends on
> > > > maintainer's flow it may be good or bad time to resend with properly
> > > > formed changelog and version of the series.
> > 
> > yeah sorry I wont look at it till merge window closes
> [>>] Sorry.
> > 
> > > [>>] Thanks. Will resend the patch set with v1 in the header.
> > 
> > Should this be v1, v1 was the first post, this would be v2!
> > 
> [>>] Thanks for the correction. I meant v2.
> > Please use git format-patch -v2 to autogenerate version headers in patches..
> > 
> > I thought Intel folks had internal review list to take care of these things, is it no
> > longer used..?
> [>>] We are, but I am confuse on what should I do to the existing patch set sent in 
> https://lore.kernel.org/dmaengine/1599213094-30144-1-git-send-email-jee.heng.sia@intel.com/. There is no response from anyone.

Sorry my bad looks like I have missed this one, can you please repost
this after merge window closes and I will look into it

Thanks
Eugeniy Paltsev Oct. 16, 2020, 2:51 p.m. UTC | #6
Hi Sia,

Is this patch series available in some public git repo?
I want to test it on our HW with DW AXI DMAC.

Thanks.
---
 Eugeniy Paltsev
Sia Jee Heng Oct. 19, 2020, 1:22 a.m. UTC | #7
> -----Original Message-----
> From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> Sent: 16 October 2020 10:51 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org; vkoul@kernel.org; Alexey Brodkin
> <Alexey.Brodkin@synopsys.com>
> Subject: Re: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> AxiDMA
> 
> Hi Sia,
> 
> Is this patch series available in some public git repo?
[>>] We do not have public git repo, but the patch series are tested on kernel v5.9
> I want to test it on our HW with DW AXI DMAC.
> 
> Thanks.
> ---
>  Eugeniy Paltsev
> 
> 
> ________________________________________
> From: Sia Jee Heng <jee.heng.sia@intel.com>
> Sent: Monday, October 12, 2020 07:21
> To: vkoul@kernel.org; Eugeniy Paltsev
> Cc: andriy.shevchenko@linux.intel.com; dmaengine@vger.kernel.org; linux-
> kernel@vger.kernel.org
> Subject: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> AxiDMA
> 
> The below patch series are to support AxiDMA running on Intel KeemBay SoC.
> The base driver is dw-axi-dmac but code refactoring is needed, for example:
> - Support YAML Schemas DT binding.
> - Replacing Linked List with virtual descriptor management.
> - Remove unrelated hw desc stuff from dma memory pool.
> - Manage dma memory pool alloc/destroy based on channel activity.
> - Support dmaengine device_sync() callback.
> - Support dmaengine device_config().
> - Support dmaegnine device_prep_slave_sg().
> - Support dmaengine device_prep_dma_cyclic().
> - Support of_dma_controller_register().
> - Support burst residue granularity.
> - Support Intel KeemBay AxiDMA registers.
> - Support Intel KeemBay AxiDMA device handshake.
> - Support Intel KeemBay AxiDMA BYTE and HALFWORD device operation.
> - Add constraint to Max segment size.
> 
> This patch set is to replace the patch series submitted at:
> https://urldefense.com/v3/__https://lore.kernel.org/dmaengine/1599213094-
> 30144-1-git-send-email-
> jee.heng.sia@intel.com/__;!!A4F2R9G_pg!Nemc1rSHID2X4d8pr0LNF0nD9Odrn4
> 25GRV8MSTPDvPwE6a3iWPeylAJSaxwqXjfPapMO4U$
> 
> This patch series are tested on Intel KeemBay platform.
> 
> 
> Sia Jee Heng (15):
>   dt-bindings: dma: Add YAML schemas for dw-axi-dmac
>   dmaengine: dw-axi-dmac: simplify descriptor management
>   dmaengine: dw-axi-dmac: move dma_pool_create() to
>     alloc_chan_resources()
>   dmaengine: dw-axi-dmac: Add device_synchronize() callback
>   dmaengine: dw-axi-dmac: Add device_config operation
>   dmaengine: dw-axi-dmac: Support device_prep_slave_sg
>   dmaegine: dw-axi-dmac: Support device_prep_dma_cyclic()
>   dmaengine: dw-axi-dmac: Support of_dma_controller_register()
>   dmaengine: dw-axi-dmac: Support burst residue granularity
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA support
>   dt-binding: dma: dw-axi-dmac: Add support for Intel KeemBay AxiDMA
>   dmaengine: dw-axi-dmac: Add Intel KeemBay DMA register fields
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA handshake
>   dmaengine: dw-axi-dmac: Add Intel KeemBay AxiDMA BYTE and HALFWORD
>     registers
>   dmaengine: dw-axi-dmac: Set constraint to the Max segment size
> 
>  .../bindings/dma/snps,dw-axi-dmac.txt         |  39 -
>  .../bindings/dma/snps,dw-axi-dmac.yaml        | 149 ++++
>  .../dma/dw-axi-dmac/dw-axi-dmac-platform.c    | 696 +++++++++++++++---
>  drivers/dma/dw-axi-dmac/dw-axi-dmac.h         |  33 +-
>  4 files changed, 783 insertions(+), 134 deletions(-)  delete mode 100644
> Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.txt
>  create mode 100644 Documentation/devicetree/bindings/dma/snps,dw-axi-
> dmac.yaml
> 
> --
> 2.18.0
Andy Shevchenko Oct. 19, 2020, 11:39 a.m. UTC | #8
On Mon, Oct 19, 2020 at 01:22:03AM +0000, Sia, Jee Heng wrote:
> > From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > Sent: 16 October 2020 10:51 PM

> > Hi Sia,
> > 
> > Is this patch series available in some public git repo?
> [>>] We do not have public git repo, but the patch series are tested on kernel v5.9

Sia, can you fork a kernel repository on GitHub or GitLab and create there a
branch with this series based on v5.9?

> > I want to test it on our HW with DW AXI DMAC.

Eugeniy, to be honest, it's not a big deal to create one either with help of
lore.kernel.org or patchwork [1].

For your convenience (disclaimer, I can't guarantee I haven't missed something
here) I published it here [2]. Note, I didn't compile it.

[1]: https://patchwork.kernel.org/project/linux-dmaengine/cover/20201012042200.29787-1-jee.heng.sia@intel.com/
[2]: https://gitlab.com/andy-shev/next/-/tree/topic/dw-dma-axi
Sia Jee Heng Oct. 21, 2020, 1:54 a.m. UTC | #9
> -----Original Message-----
> From: andriy.shevchenko@linux.intel.com
> <andriy.shevchenko@linux.intel.com>
> Sent: 19 October 2020 7:39 PM
> To: Sia, Jee Heng <jee.heng.sia@intel.com>
> Cc: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>;
> dmaengine@vger.kernel.org; linux-kernel@vger.kernel.org; vkoul@kernel.org;
> Alexey Brodkin <Alexey.Brodkin@synopsys.com>
> Subject: Re: [PATCH 00/15] dmaengine: dw-axi-dmac: support Intel KeemBay
> AxiDMA
> 
> On Mon, Oct 19, 2020 at 01:22:03AM +0000, Sia, Jee Heng wrote:
> > > From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
> > > Sent: 16 October 2020 10:51 PM
> 
> > > Hi Sia,
> > >
> > > Is this patch series available in some public git repo?
> > [>>] We do not have public git repo, but the patch series are tested
> > on kernel v5.9
> 
> Sia, can you fork a kernel repository on GitHub or GitLab and create there a
> branch with this series based on v5.9?
[>>] Thanks Andy to help to create branch at https://gitlab.com/andy-shev/next/-/tree/topic/dw-dma-axi.
Eugeniy, you can start to use this branch and I shall learn to create a public repo. Do let me know if you need anything else.
> 
> > > I want to test it on our HW with DW AXI DMAC.
> 
> Eugeniy, to be honest, it's not a big deal to create one either with help of
> lore.kernel.org or patchwork [1].
> 
> For your convenience (disclaimer, I can't guarantee I haven't missed something
> here) I published it here [2]. Note, I didn't compile it.
> 
> [1]: https://patchwork.kernel.org/project/linux-
> dmaengine/cover/20201012042200.29787-1-jee.heng.sia@intel.com/
> [2]: https://gitlab.com/andy-shev/next/-/tree/topic/dw-dma-axi
> 
> --
> With Best Regards,
> Andy Shevchenko
>