[3/4] irqchip/mbigen: add support for a MBIGEN generating SPIs
diff mbox series

Message ID 1539681316-19300-4-git-send-email-yangyingliang@huawei.com
State Superseded
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Series
  • add support for MBIGEN generating message based SPIs
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Commit Message

Yang Yingliang Oct. 16, 2018, 9:15 a.m. UTC
Now with
5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR.

The first 64-pins of each MBIGEN chip is used to generate SPIs, and each
MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating
LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate
the pin index in a unified way in mbigen_domain_translate().

Also Add TYPE and VEC registers that used by generating SPIs, the driver can
access them when MBIGEN is used to generate SPIs.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
---
 drivers/irqchip/irq-mbigen.c | 21 +++++++++++++++++++--
 1 file changed, 19 insertions(+), 2 deletions(-)

Comments

Marc Zyngier Oct. 17, 2018, 4:30 p.m. UTC | #1
On 16/10/18 10:15, Yang Yingliang wrote:
> Now with
> 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
> we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR.
> 
> The first 64-pins of each MBIGEN chip is used to generate SPIs, and each
> MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating
> LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate
> the pin index in a unified way in mbigen_domain_translate().
> 
> Also Add TYPE and VEC registers that used by generating SPIs, the driver can
> access them when MBIGEN is used to generate SPIs.
> 
> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
> ---
>  drivers/irqchip/irq-mbigen.c | 21 +++++++++++++++++++--
>  1 file changed, 19 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
> index f05998f..37c1932 100644
> --- a/drivers/irqchip/irq-mbigen.c
> +++ b/drivers/irqchip/irq-mbigen.c
> @@ -48,6 +48,7 @@
>  #define MBIGEN_NODE_OFFSET		0x1000
>  
>  /* offset of vector register in mbigen node */
> +#define REG_MBIGEN_SPI_VEC_OFFSET	0x500
>  #define REG_MBIGEN_LPI_VEC_OFFSET	0x200
>  
>  /**
> @@ -62,6 +63,7 @@
>   * This register is used to configure interrupt
>   * trigger type
>   */
> +#define REG_MBIGEN_SPI_TYPE_OFFSET	0x400
>  #define REG_MBIGEN_LPI_TYPE_OFFSET	0x0
>  
>  /**
> @@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
>  {
>  	unsigned int nid, pin;
>  
> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP)
> +		return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET);
> +
>  	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>  	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>  	pin = hwirq % IRQS_PER_MBIGEN_NODE;
> @@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
>  {
>  	unsigned int nid, irq_ofst, ofst;
>  
> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
> +		*mask = 1 << (hwirq % 32);
> +		ofst = hwirq / 32 * 4;
> +		*addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET;
> +		return;
> +	}
> +
>  	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>  	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>  	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
> @@ -162,6 +174,12 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
>  	u32 val;
>  
>  	base += get_mbigen_vec_reg(d->hwirq);
> +
> +	if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
> +		writel_relaxed(msg->data, base);
> +		return;
> +	}

How is the GICD_SETSPI_NSR base address programmed if you're ignoring
the address stored in the message?

How do you deal with level interrupts, as you don't seem to use the
level MSI framework either?

> +
>  	val = readl_relaxed(base);
>  
>  	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
> @@ -182,8 +200,7 @@ static int mbigen_domain_translate(struct irq_domain *d,
>  		if (fwspec->param_count != 2)
>  			return -EINVAL;
>  
> -		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
> -			(fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
> +		if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
>  			return -EINVAL;
>  		else
>  			*hwirq = fwspec->param[0];
> 

Now, the biggest question of them all: how does it work with ACPI? Last
time I checked, there was no DT support for platforms using the MBIGEN.

My gut feeling is that it would be so much better if the SPIs generated
by the MBIGEN were configured in firmware, and the devices behind it
would just describe the corresponding SPI...

Thanks,

	M.
Yang Yingliang Oct. 18, 2018, 3:41 a.m. UTC | #2
Hi, Marc

On 2018/10/18 0:30, Marc Zyngier wrote:
> On 16/10/18 10:15, Yang Yingliang wrote:
>> Now with
>> 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
>> we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR.
>>
>> The first 64-pins of each MBIGEN chip is used to generate SPIs, and each
>> MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating
>> LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate
>> the pin index in a unified way in mbigen_domain_translate().
>>
>> Also Add TYPE and VEC registers that used by generating SPIs, the driver can
>> access them when MBIGEN is used to generate SPIs.
>>
>> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
>> ---
>>   drivers/irqchip/irq-mbigen.c | 21 +++++++++++++++++++--
>>   1 file changed, 19 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
>> index f05998f..37c1932 100644
>> --- a/drivers/irqchip/irq-mbigen.c
>> +++ b/drivers/irqchip/irq-mbigen.c
>> @@ -48,6 +48,7 @@
>>   #define MBIGEN_NODE_OFFSET		0x1000
>>   
>>   /* offset of vector register in mbigen node */
>> +#define REG_MBIGEN_SPI_VEC_OFFSET	0x500
>>   #define REG_MBIGEN_LPI_VEC_OFFSET	0x200
>>   
>>   /**
>> @@ -62,6 +63,7 @@
>>    * This register is used to configure interrupt
>>    * trigger type
>>    */
>> +#define REG_MBIGEN_SPI_TYPE_OFFSET	0x400
>>   #define REG_MBIGEN_LPI_TYPE_OFFSET	0x0
>>   
>>   /**
>> @@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
>>   {
>>   	unsigned int nid, pin;
>>   
>> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP)
>> +		return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET);
>> +
>>   	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>>   	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>>   	pin = hwirq % IRQS_PER_MBIGEN_NODE;
>> @@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
>>   {
>>   	unsigned int nid, irq_ofst, ofst;
>>   
>> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
>> +		*mask = 1 << (hwirq % 32);
>> +		ofst = hwirq / 32 * 4;
>> +		*addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET;
>> +		return;
>> +	}
>> +
>>   	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>>   	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>>   	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
>> @@ -162,6 +174,12 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
>>   	u32 val;
>>   
>>   	base += get_mbigen_vec_reg(d->hwirq);
>> +
>> +	if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
>> +		writel_relaxed(msg->data, base);
>> +		return;
>> +	}
> How is the GICD_SETSPI_NSR base address programmed if you're ignoring
> the address stored in the message?
Now, this base address is encoded in MBIGEN register by default.

In case this address isn't set to register in later SoCs, I think the
MBIGEN driver set this base address would be better. I will add
relative codes to handle both GICD_SETSPI_NSR and ITS Translate
address.

>
> How do you deal with level interrupts, as you don't seem to use the
> level MSI framework either?
The MBIGEN driver need to clear active state in irq_eoi hook, when it
dealing with level SPIs.

>
>> +
>>   	val = readl_relaxed(base);
>>   
>>   	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
>> @@ -182,8 +200,7 @@ static int mbigen_domain_translate(struct irq_domain *d,
>>   		if (fwspec->param_count != 2)
>>   			return -EINVAL;
>>   
>> -		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
>> -			(fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
>> +		if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
>>   			return -EINVAL;
>>   		else
>>   			*hwirq = fwspec->param[0];
>>
> Now, the biggest question of them all: how does it work with ACPI? Last
> time I checked, there was no DT support for platforms using the MBIGEN.
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
This DT describes how platform devices using the MBIGEN.

>
> My gut feeling is that it would be so much better if the SPIs generated
> by the MBIGEN were configured in firmware, and the devices behind it
> would just describe the corresponding SPI...
We need use this framework to clear active state in MBIGEN register, so 
configuring
in firmware is not enough...

Regards,
Yang
>
> Thanks,
>
> 	M.
Marc Zyngier Oct. 18, 2018, 8:55 a.m. UTC | #3
Hi Yang,

On 18/10/18 04:41, Yang Yingliang wrote:
> Hi, Marc
> 
> On 2018/10/18 0:30, Marc Zyngier wrote:
>> On 16/10/18 10:15, Yang Yingliang wrote:
>>> Now with
>>> 5052875 ("irqchip/gic-v3: Add support for Message Based Interrupts as an MSI controller"),
>>> we can support MBIGEN to generate message based SPIs by writing GICD_SETSPIR.
>>>
>>> The first 64-pins of each MBIGEN chip is used to generate SPIs, and each
>>> MBIGEN chip has several MBIGEN nodes, every node has 128 pins for generating
>>> LPIs. The total pins are: 64(SPIs) + 128 * node_nr(LPIs). So we can translate
>>> the pin index in a unified way in mbigen_domain_translate().
>>>
>>> Also Add TYPE and VEC registers that used by generating SPIs, the driver can
>>> access them when MBIGEN is used to generate SPIs.
>>>
>>> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
>>> ---
>>>   drivers/irqchip/irq-mbigen.c | 21 +++++++++++++++++++--
>>>   1 file changed, 19 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
>>> index f05998f..37c1932 100644
>>> --- a/drivers/irqchip/irq-mbigen.c
>>> +++ b/drivers/irqchip/irq-mbigen.c
>>> @@ -48,6 +48,7 @@
>>>   #define MBIGEN_NODE_OFFSET		0x1000
>>>   
>>>   /* offset of vector register in mbigen node */
>>> +#define REG_MBIGEN_SPI_VEC_OFFSET	0x500
>>>   #define REG_MBIGEN_LPI_VEC_OFFSET	0x200
>>>   
>>>   /**
>>> @@ -62,6 +63,7 @@
>>>    * This register is used to configure interrupt
>>>    * trigger type
>>>    */
>>> +#define REG_MBIGEN_SPI_TYPE_OFFSET	0x400
>>>   #define REG_MBIGEN_LPI_TYPE_OFFSET	0x0
>>>   
>>>   /**
>>> @@ -79,6 +81,9 @@ static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
>>>   {
>>>   	unsigned int nid, pin;
>>>   
>>> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP)
>>> +		return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET);
>>> +
>>>   	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>>>   	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>>>   	pin = hwirq % IRQS_PER_MBIGEN_NODE;
>>> @@ -92,6 +97,13 @@ static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
>>>   {
>>>   	unsigned int nid, irq_ofst, ofst;
>>>   
>>> +	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
>>> +		*mask = 1 << (hwirq % 32);
>>> +		ofst = hwirq / 32 * 4;
>>> +		*addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET;
>>> +		return;
>>> +	}
>>> +
>>>   	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
>>>   	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
>>>   	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
>>> @@ -162,6 +174,12 @@ static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
>>>   	u32 val;
>>>   
>>>   	base += get_mbigen_vec_reg(d->hwirq);
>>> +
>>> +	if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
>>> +		writel_relaxed(msg->data, base);
>>> +		return;
>>> +	}
>> How is the GICD_SETSPI_NSR base address programmed if you're ignoring
>> the address stored in the message?
> Now, this base address is encoded in MBIGEN register by default.

OK. So let's move the comment in that function to the top, and indicate
that this also applies to the GICD_SETSPI_NSR register.

> In case this address isn't set to register in later SoCs, I think the
> MBIGEN driver set this base address would be better. I will add
> relative codes to handle both GICD_SETSPI_NSR and ITS Translate
> address.
> 
>>
>> How do you deal with level interrupts, as you don't seem to use the
>> level MSI framework either?
> The MBIGEN driver need to clear active state in irq_eoi hook, when it
> dealing with level SPIs.

OK, so you're not taking advantage of the the CLEAR register here? Sad.

> 
>>
>>> +
>>>   	val = readl_relaxed(base);
>>>   
>>>   	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
>>> @@ -182,8 +200,7 @@ static int mbigen_domain_translate(struct irq_domain *d,
>>>   		if (fwspec->param_count != 2)
>>>   			return -EINVAL;
>>>   
>>> -		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
>>> -			(fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
>>> +		if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
>>>   			return -EINVAL;
>>>   		else
>>>   			*hwirq = fwspec->param[0];
>>>
>> Now, the biggest question of them all: how does it work with ACPI? Last
>> time I checked, there was no DT support for platforms using the MBIGEN.
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
> This DT describes how platform devices using the MBIGEN.

That's not how my own D05 boots. It is ACPI only. How is that going to
work on this platform?

> 
>>
>> My gut feeling is that it would be so much better if the SPIs generated
>> by the MBIGEN were configured in firmware, and the devices behind it
>> would just describe the corresponding SPI...
> We need use this framework to clear active state in MBIGEN register, so 
> configuring
> in firmware is not enough...

Fair enough.

Thanks,

	M.
Hanjun Guo Oct. 18, 2018, 11:20 a.m. UTC | #4
Hi Marc,

>>>>
>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>> time I checked, there was no DT support for platforms using the MBIGEN.
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
>> This DT describes how platform devices using the MBIGEN.
> 
> That's not how my own D05 boots. It is ACPI only. How is that going to
> work on this platform?

D05 is ACPI only so it has no dtb in the firmware, that's why we can
boot D05 without acpi=on in the boot cmdline, but if you want to
boot D05 with dtb, you could try to specify the dtb in the grub
(seems centos based):

menuentry "example" --id example{
        linux /Image-kernel root=... rdinit=...
        initrd /example.img
        devicetree /d05.dtb
}

Hope it helps.

Thanks
Hanjun
Marc Zyngier Oct. 18, 2018, 11:56 a.m. UTC | #5
Hi Hanjun,

On 18/10/18 12:20, Hanjun Guo wrote:
> Hi Marc,
> 
>>>>>
>>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>>> time I checked, there was no DT support for platforms using the MBIGEN.
>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
>>> This DT describes how platform devices using the MBIGEN.
>>
>> That's not how my own D05 boots. It is ACPI only. How is that going to
>> work on this platform?
> 
> D05 is ACPI only so it has no dtb in the firmware, that's why we can
> boot D05 without acpi=on in the boot cmdline, but if you want to
> boot D05 with dtb, you could try to specify the dtb in the grub
> (seems centos based):
> 
> menuentry "example" --id example{
>         linux /Image-kernel root=... rdinit=...
>         initrd /example.img
>         devicetree /d05.dtb
> }

Sure. But what I'm asking here is how this change in the MBIGEN driver
can be beneficial to people who need ACPI, for better or worse? For
example, you cannot get the PCIe SMMU without ACPI. Good-bye VFIO.

If it is DT only, I seriously doubt anyone will be able to use it.

Thanks,

	M.
Hanjun Guo Oct. 18, 2018, 12:54 p.m. UTC | #6
On 2018/10/18 19:56, Marc Zyngier wrote:
> Hi Hanjun,
> 
> On 18/10/18 12:20, Hanjun Guo wrote:
>> Hi Marc,
>>
>>>>>>
>>>>> Now, the biggest question of them all: how does it work with ACPI? Last
>>>>> time I checked, there was no DT support for platforms using the MBIGEN.
>>>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/hisilicon/hip07.dtsi
>>>> This DT describes how platform devices using the MBIGEN.
>>>
>>> That's not how my own D05 boots. It is ACPI only. How is that going to
>>> work on this platform?
>>
>> D05 is ACPI only so it has no dtb in the firmware, that's why we can
>> boot D05 without acpi=on in the boot cmdline, but if you want to
>> boot D05 with dtb, you could try to specify the dtb in the grub
>> (seems centos based):
>>
>> menuentry "example" --id example{
>>         linux /Image-kernel root=... rdinit=...
>>         initrd /example.img
>>         devicetree /d05.dtb
>> }
> 
> Sure. But what I'm asking here is how this change in the MBIGEN driver
> can be beneficial to people who need ACPI, for better or worse? For
> example, you cannot get the PCIe SMMU without ACPI. Good-bye VFIO.
> 
> If it is DT only, I seriously doubt anyone will be able to use it.

We have another ARM64 SoC for wireless base station which with the
same CPU DIE but different IO DIE, they share the same mbigen controller.

Since we use big-endian on wireless base station so only DT is available
(EFI stub is little-endian), we need to reuse this mbigen driver
on this SoC (not the one for D05) as well, not sure if this makes sense
to you, please let us know.

Thanks
Hanjun

Patch
diff mbox series

diff --git a/drivers/irqchip/irq-mbigen.c b/drivers/irqchip/irq-mbigen.c
index f05998f..37c1932 100644
--- a/drivers/irqchip/irq-mbigen.c
+++ b/drivers/irqchip/irq-mbigen.c
@@ -48,6 +48,7 @@ 
 #define MBIGEN_NODE_OFFSET		0x1000
 
 /* offset of vector register in mbigen node */
+#define REG_MBIGEN_SPI_VEC_OFFSET	0x500
 #define REG_MBIGEN_LPI_VEC_OFFSET	0x200
 
 /**
@@ -62,6 +63,7 @@ 
  * This register is used to configure interrupt
  * trigger type
  */
+#define REG_MBIGEN_SPI_TYPE_OFFSET	0x400
 #define REG_MBIGEN_LPI_TYPE_OFFSET	0x0
 
 /**
@@ -79,6 +81,9 @@  static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
 {
 	unsigned int nid, pin;
 
+	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP)
+		return (hwirq * 4 + REG_MBIGEN_SPI_VEC_OFFSET);
+
 	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
 	pin = hwirq % IRQS_PER_MBIGEN_NODE;
@@ -92,6 +97,13 @@  static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
 {
 	unsigned int nid, irq_ofst, ofst;
 
+	if (hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
+		*mask = 1 << (hwirq % 32);
+		ofst = hwirq / 32 * 4;
+		*addr = ofst + REG_MBIGEN_SPI_TYPE_OFFSET;
+		return;
+	}
+
 	hwirq -= SPI_NUM_PER_MBIGEN_CHIP;
 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
 	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
@@ -162,6 +174,12 @@  static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
 	u32 val;
 
 	base += get_mbigen_vec_reg(d->hwirq);
+
+	if (d->hwirq < SPI_NUM_PER_MBIGEN_CHIP) {
+		writel_relaxed(msg->data, base);
+		return;
+	}
+
 	val = readl_relaxed(base);
 
 	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
@@ -182,8 +200,7 @@  static int mbigen_domain_translate(struct irq_domain *d,
 		if (fwspec->param_count != 2)
 			return -EINVAL;
 
-		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
-			(fwspec->param[0] < SPI_NUM_PER_MBIGEN_CHIP))
+		if (fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM)
 			return -EINVAL;
 		else
 			*hwirq = fwspec->param[0];