From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH v6 20/20] powerpc/mm: reintroduce 16K pages with HW assistance on 8xx
Date: Fri, 19 Oct 2018 06:55:32 +0000 (UTC) [thread overview]
Message-ID: <e6d55509dbb979da8c1a3a2b704d300d2f4e19d2.1539931703.git.christophe.leroy@c-s.fr> (raw)
In-Reply-To: <cover.1539931702.git.christophe.leroy@c-s.fr>
Using this HW assistance implies some constraints on the
page table structure:
- Regardless of the main page size used (4k or 16k), the
level 1 table (PGD) contains 1024 entries and each PGD entry covers
a 4Mbytes area which is managed by a level 2 table (PTE) containing
also 1024 entries each describing a 4k page.
- 16k pages require 4 identifical entries in the L2 table
- 512k pages PTE have to be spread every 128 bytes in the L2 table
- 8M pages PTE are at the address pointed by the L1 entry and each
8M page require 2 identical entries in the PGD.
In order to use hardware assistance with 16K pages, this patch does
the following modifications:
- Make PGD size independent of the main page size
- In 16k pages mode, redefine pte_t as a struct with 4 elements,
and populate those 4 elements in __set_pte_at() and pte_update()
- Adapt the size of the hugepage tables.
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/Kconfig | 2 +-
arch/powerpc/include/asm/nohash/32/pgtable.h | 18 +++++++++++++++++-
arch/powerpc/include/asm/nohash/pgtable.h | 4 ++++
arch/powerpc/include/asm/pgtable-types.h | 4 ++++
4 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 287befcf37ab..3d008115fe18 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -690,7 +690,7 @@ config PPC_4K_PAGES
config PPC_16K_PAGES
bool "16k page size"
- depends on 44x
+ depends on 44x || PPC_8xx
config PPC_64K_PAGES
bool "64k page size"
diff --git a/arch/powerpc/include/asm/nohash/32/pgtable.h b/arch/powerpc/include/asm/nohash/32/pgtable.h
index c33fbbb7ce82..19941fb8d690 100644
--- a/arch/powerpc/include/asm/nohash/32/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/32/pgtable.h
@@ -19,9 +19,15 @@ extern int icache_44x_need_flush;
#endif /* __ASSEMBLY__ */
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+#define PTE_INDEX_SIZE (PTE_SHIFT - 2)
+#define PTE_FRAG_NR 4
+#define PTE_FRAG_SIZE_SHIFT 12
+#else
#define PTE_INDEX_SIZE PTE_SHIFT
#define PTE_FRAG_NR 1
#define PTE_FRAG_SIZE_SHIFT PAGE_SHIFT
+#endif
#define PTE_FRAG_SIZE (1UL << PTE_FRAG_SIZE_SHIFT)
#define PMD_INDEX_SIZE 0
@@ -52,7 +58,11 @@ extern int icache_44x_need_flush;
* -Matt
*/
/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#ifdef CONFIG_PPC_8xx
+#define PGDIR_SHIFT 22
+#else
#define PGDIR_SHIFT (PAGE_SHIFT + PTE_INDEX_SIZE)
+#endif
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
@@ -236,7 +246,13 @@ static inline unsigned long pte_update(pte_t *p,
: "cc" );
#else /* PTE_ATOMIC_UPDATES */
unsigned long old = pte_val(*p);
- *p = __pte((old & ~clr) | set);
+ unsigned long new = (old & ~clr) | set;
+
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+ p->pte = p->pte1 = p->pte2 = p->pte3 = new;
+#else
+ *p = __pte(new);
+#endif
#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
diff --git a/arch/powerpc/include/asm/nohash/pgtable.h b/arch/powerpc/include/asm/nohash/pgtable.h
index 70ff23974b59..1ca1c1864b32 100644
--- a/arch/powerpc/include/asm/nohash/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/pgtable.h
@@ -209,7 +209,11 @@ static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
/* Anything else just stores the PTE normally. That covers all 64-bit
* cases, and 32-bit non-hash with 32-bit PTEs.
*/
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+ ptep->pte = ptep->pte1 = ptep->pte2 = ptep->pte3 = pte_val(pte);
+#else
*ptep = pte;
+#endif
/*
* With hardware tablewalk, a sync is needed to ensure that
diff --git a/arch/powerpc/include/asm/pgtable-types.h b/arch/powerpc/include/asm/pgtable-types.h
index eccb30b38b47..3b0edf041b2e 100644
--- a/arch/powerpc/include/asm/pgtable-types.h
+++ b/arch/powerpc/include/asm/pgtable-types.h
@@ -3,7 +3,11 @@
#define _ASM_POWERPC_PGTABLE_TYPES_H
/* PTE level */
+#if defined(CONFIG_PPC_8xx) && defined(CONFIG_PPC_16K_PAGES)
+typedef struct { pte_basic_t pte, pte1, pte2, pte3; } pte_t;
+#else
typedef struct { pte_basic_t pte; } pte_t;
+#endif
#define __pte(x) ((pte_t) { (x) })
static inline pte_basic_t pte_val(pte_t x)
{
--
2.13.3
prev parent reply other threads:[~2018-10-19 6:55 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-19 6:54 [PATCH v6 00/20] Implement use of HW assistance on TLB table walk on 8xx Christophe Leroy
2018-10-19 6:54 ` [PATCH v6 01/20] Revert "powerpc/8xx: Use L1 entry APG to handle _PAGE_ACCESSED for CONFIG_SWAP" Christophe Leroy
2018-10-31 5:42 ` [v6, " Michael Ellerman
2018-10-19 6:54 ` [PATCH v6 02/20] powerpc/mm: Move pte_fragment_alloc() to a common location Christophe Leroy
2018-10-19 6:54 ` [PATCH v6 03/20] powerpc/mm: Avoid useless lock with single page fragments Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 04/20] powerpc/mm: move platform specific mmu-xxx.h in platform directories Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 05/20] powerpc/mm: Move pgtable_t into platform headers Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 06/20] powerpc/code-patching: add a helper to get the address of a patch_site Christophe Leroy
2018-10-31 5:42 ` [v6, " Michael Ellerman
2018-10-19 6:55 ` [PATCH v6 07/20] powerpc/8xx: Use patch_site for memory setup patching Christophe Leroy
2018-10-31 5:42 ` [v6,07/20] " Michael Ellerman
2018-10-19 6:55 ` [PATCH v6 08/20] powerpc/8xx: Use patch_site for perf counters setup Christophe Leroy
2018-10-31 5:42 ` [v6,08/20] " Michael Ellerman
2018-10-19 6:55 ` [PATCH v6 09/20] powerpc/8xx: Move SW perf counters in first 32kb of memory Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 10/20] powerpc/8xx: Temporarily disable 16k pages and 512k hugepages Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 11/20] powerpc/mm: Use hardware assistance in TLB handlers on the 8xx Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 12/20] powerpc/mm: Enable 512k hugepage support with HW assistance " Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 13/20] powerpc/8xx: don't use r12/SPRN_SPRG_SCRATCH2 in TLB Miss handlers Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 14/20] powerpc/8xx: regroup TLB handler routines Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 15/20] powerpc/mm: don't use pte_alloc_one_kernel() before slab is available Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 16/20] powerpc/mm: inline pte_alloc_one() and pte_alloc_one_kernel() in PPC32 Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 17/20] powerpc/book3s32: Remove CONFIG_BOOKE dependent code Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 18/20] powerpc/mm: Extend pte_fragment functionality to nohash/32 Christophe Leroy
2018-10-19 6:55 ` [PATCH v6 19/20] powerpc/8xx: Remove PTE_ATOMIC_UPDATES Christophe Leroy
2018-10-19 6:55 ` Christophe Leroy [this message]
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