From: Christophe Leroy <christophe.leroy@c-s.fr>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
Paul Mackerras <paulus@samba.org>,
Michael Ellerman <mpe@ellerman.id.au>
Cc: linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org
Subject: [PATCH 4/9] powerpc/book3s/32: Use MMU_FTR_HPTE_TABLE in head_32.S
Date: Fri, 9 Nov 2018 17:33:22 +0000 (UTC) [thread overview]
Message-ID: <d011001c94681a20a0c836ae3a9bf5e4f4d7a38e.1541784640.git.christophe.leroy@c-s.fr> (raw)
In-Reply-To: <e63d9ac8ef6e83fc243d8910d7c789e111e48580.1541784640.git.christophe.leroy@c-s.fr>
Instead of manually patching a blr at hash_page() entry in
MMU_init_hw(), this patch adds a features section in head_32.S
Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
arch/powerpc/kernel/head_32.S | 4 ++++
arch/powerpc/mm/ppc_mmu_32.c | 12 +-----------
2 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S
index 61ca27929355..068c1656c758 100644
--- a/arch/powerpc/kernel/head_32.S
+++ b/arch/powerpc/kernel/head_32.S
@@ -393,7 +393,9 @@ DataAccess:
bne 1f /* if not, try to put a PTE */
mfspr r4,SPRN_DAR /* into the hash table */
rlwinm r3,r10,32-15,21,21 /* DSISR_STORE -> _PAGE_RW */
+BEGIN_MMU_FTR_SECTION
bl hash_page
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
1: lwz r5,_DSISR(r11) /* get DSISR value */
mfspr r4,SPRN_DAR
EXC_XFER_LITE(0x300, handle_page_fault)
@@ -408,7 +410,9 @@ InstructionAccess:
beq 1f /* if so, try to put a PTE */
li r3,0 /* into the hash table */
mr r4,r12 /* SRR0 is fault address */
+BEGIN_MMU_FTR_SECTION
bl hash_page
+END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
1: mr r4,r12
andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
EXC_XFER_LITE(0x400, handle_page_fault)
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c
index f6f575bae3bc..3c7c73defcb6 100644
--- a/arch/powerpc/mm/ppc_mmu_32.c
+++ b/arch/powerpc/mm/ppc_mmu_32.c
@@ -184,20 +184,10 @@ void __init MMU_init_hw(void)
extern unsigned int hash_page_patch_A[];
extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
- extern unsigned int hash_page[];
extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
- if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
- /*
- * Put a blr (procedure return) instruction at the
- * start of hash_page, since we can still get DSI
- * exceptions on a 603.
- */
- hash_page[0] = 0x4e800020;
- flush_icache_range((unsigned long) &hash_page[0],
- (unsigned long) &hash_page[1]);
+ if (!mmu_has_feature(MMU_FTR_HPTE_TABLE))
return;
- }
if ( ppc_md.progress ) ppc_md.progress("hash:enter", 0x105);
--
2.13.3
next prev parent reply other threads:[~2018-11-09 17:33 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-09 17:33 [PATCH 1/9] powerpc: simplify patch_instruction_site() and patch_branch_site() Christophe Leroy
2018-11-09 17:33 ` [PATCH 2/9] powerpc: add modify_instruction() and modify_instruction_site() Christophe Leroy
2018-11-09 17:33 ` [PATCH 3/9] powerpc/32: use patch_site_addr() in machine_init() Christophe Leroy
2018-11-09 17:33 ` Christophe Leroy [this message]
2018-11-09 17:33 ` [PATCH 5/9] powerpc/book3s/32: Use patch_site to patch hash functions Christophe Leroy
2018-11-09 17:33 ` [PATCH 6/9] powerpc/8xx: use modify_instruction_site() Christophe Leroy
2018-11-09 17:33 ` [PATCH 7/9] powerpc/signal: Use code patching instead of hardcoding Christophe Leroy
2018-11-09 17:33 ` [PATCH 8/9] powerpc/44x: use patch_sites for TLB handlers patching Christophe Leroy
2018-11-09 17:33 ` [PATCH 9/9] powerpc/smp: Use code patching to restore reset vector Christophe Leroy
2018-12-22 9:55 ` [1/9] powerpc: simplify patch_instruction_site() and patch_branch_site() Michael Ellerman
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