From: Borislav Petkov <bp@alien8.de>
To: X86 ML <x86@kernel.org>
Cc: LKML <linux-kernel@vger.kernel.org>,
Andy Lutomirski <luto@kernel.org>,
"H. Peter Anvin" <hpa@zytor.com>,
John Stultz <john.stultz@linaro.org>,
Thomas Lendacky <Thomas.Lendacky@amd.com>
Subject: [PATCH] x86/TSC: Use RDTSCP
Date: Mon, 19 Nov 2018 19:45:56 +0100 [thread overview]
Message-ID: <20181119184556.11479-1-bp@alien8.de> (raw)
From: Borislav Petkov <bp@suse.de>
Currently, the kernel uses
[LM]FENCE; RDTSC
in the timekeeping code, to guarantee monotonicity of time where the
*FENCE is selected based on vendor.
Replace that sequence with RDTSCP which is faster or on-par and gives
the same guarantees.
A microbenchmark on Intel shows that the change is on-par.
On AMD, the change is either on-par with the current LFENCE-prefixed
RDTSC and some are slightly better with RDTSCP.
The comparison is done with the LFENCE-prefixed RDTSC (and not with the
MFENCE-prefixed one, as one would normally expect) because all modern
AMD families make LFENCE serializing and thus avoid the heavy MFENCE by
effectively enabling X86_FEATURE_LFENCE_RDTSC.
Co-developed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Andy Lutomirski <luto@kernel.org>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: John Stultz <john.stultz@linaro.org>
Cc: Thomas Lendacky <Thomas.Lendacky@amd.com>
Cc: x86@kernel.org
---
arch/x86/include/asm/msr.h | 15 +++++++++++++--
1 file changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/msr.h b/arch/x86/include/asm/msr.h
index 91e4cf189914..f00f2b61d326 100644
--- a/arch/x86/include/asm/msr.h
+++ b/arch/x86/include/asm/msr.h
@@ -217,6 +217,8 @@ static __always_inline unsigned long long rdtsc(void)
*/
static __always_inline unsigned long long rdtsc_ordered(void)
{
+ DECLARE_ARGS(val, low, high);
+
/*
* The RDTSC instruction is not ordered relative to memory
* access. The Intel SDM and the AMD APM are both vague on this
@@ -227,9 +229,18 @@ static __always_inline unsigned long long rdtsc_ordered(void)
* ordering guarantees as reading from a global memory location
* that some other imaginary CPU is updating continuously with a
* time stamp.
+ *
+ * Thus, use the preferred barrier on the respective CPU, aiming for
+ * RDTSCP as the default.
*/
- barrier_nospec();
- return rdtsc();
+ asm volatile(ALTERNATIVE_2("mfence; rdtsc",
+ "lfence; rdtsc", X86_FEATURE_LFENCE_RDTSC,
+ "rdtscp", X86_FEATURE_RDTSCP)
+ : EAX_EDX_RET(val, low, high)
+ /* RDTSCP clobbers ECX with MSR_TSC_AUX. */
+ :: "ecx");
+
+ return EAX_EDX_VAL(val, low, high);
}
static inline unsigned long long native_read_pmc(int counter)
--
2.19.1
next reply other threads:[~2018-11-19 18:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-19 18:45 Borislav Petkov [this message]
2018-11-19 19:02 ` [PATCH] x86/TSC: Use RDTSCP Lendacky, Thomas
2018-11-19 19:52 ` Andy Lutomirski
2018-11-19 20:17 ` H. Peter Anvin
2018-11-19 20:40 ` Borislav Petkov
2018-11-19 20:48 ` hpa
2018-11-20 9:11 ` [tip:x86/timers] " tip-bot for Borislav Petkov
2018-11-23 20:03 ` [PATCH] " Guenter Roeck
2018-11-23 20:22 ` hpa
2018-11-23 20:44 ` Thomas Gleixner
2018-11-23 20:44 ` Borislav Petkov
2018-11-23 21:03 ` Guenter Roeck
2018-11-23 21:07 ` Borislav Petkov
2018-12-07 18:39 ` Borislav Petkov
2019-01-16 11:59 ` [tip:x86/alternatives] " tip-bot for Borislav Petkov
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