From: Wesley Sheng <wesley.sheng@microchip.com>
To: <kurt.schwemmer@microsemi.com>, <logang@deltatee.com>,
<jdmason@kudzu.us>, <dave.jiang@intel.com>, <allenbh@gmail.com>,
<linux-pci@vger.kernel.org>, <linux-ntb@googlegroups.com>,
<linux-kernel@vger.kernel.org>
Cc: <wesleyshenggit@sina.com>, <wesley.sheng@microchip.com>
Subject: [PATCH 3/3] ntb_hw_switchtec: NT req id mapping table register entry number should be 512
Date: Thu, 22 Nov 2018 17:02:02 +0800 [thread overview]
Message-ID: <1542877322-24548-4-git-send-email-wesley.sheng@microchip.com> (raw)
In-Reply-To: <1542877322-24548-1-git-send-email-wesley.sheng@microchip.com>
The number of available NT req id mapping table entries per NTB control
register is 512. The driver mistakenly limits the number to 256.
Fix the array size of NT req id mapping table.
Signed-off-by: Wesley Sheng <wesley.sheng@microchip.com>
---
include/linux/switchtec.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/linux/switchtec.h b/include/linux/switchtec.h
index 1e6e333..52a079b 100644
--- a/include/linux/switchtec.h
+++ b/include/linux/switchtec.h
@@ -253,8 +253,8 @@ struct ntb_ctrl_regs {
u32 reserved[3];
} bar_ext_entry[6];
u32 reserved2[192];
- u32 req_id_table[256];
- u32 reserved3[512];
+ u32 req_id_table[512];
+ u32 reserved3[256];
u64 lut_entry[512];
} __packed;
--
2.7.4
next prev parent reply other threads:[~2018-11-22 3:04 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-22 9:01 [PATCH 0/3] ntb_hw_switchtec: Added support of >=4G memory windows Wesley Sheng
2018-11-22 9:02 ` [PATCH 1/3] ntb_hw_switchtec: debug print 64bit aligned crosslink BAR Numbers Wesley Sheng
2018-11-22 9:02 ` [PATCH 2/3] ntb_hw_switchtec: Added support of >=4G memory windows Wesley Sheng
2018-11-23 15:49 ` kbuild test robot
2018-11-27 16:06 ` Jon Mason
2018-11-22 9:02 ` Wesley Sheng [this message]
2018-11-22 16:54 ` [PATCH 0/3] " Logan Gunthorpe
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