From: Peter Zijlstra <peterz@infradead.org>
To: dave.hansen@intel.com, luto@kernel.org, peterz@infradead.org
Cc: x86@kernel.org, Tom.StDenis@amd.com, linux-kernel@vger.kernel.org
Subject: [PATCH 4/4] x86/mm/cpa: Better use clflushopt
Date: Fri, 30 Nov 2018 14:44:59 +0100 [thread overview]
Message-ID: <20181130140337.662216603@infradead.org> (raw)
In-Reply-To: 20181130134455.490139778@infradead.org
[-- Attachment #1: peterz-cpa-clflush_opt.patch --]
[-- Type: text/plain, Size: 2222 bytes --]
Currently we issue an MFENCE before and after flushing a range. This
means that if we flush a bunch of single page ranges -- like with the
cpa array, we issue a whole bunch of superfluous MFENCEs.
Reorgainze the code a little to avoid this.
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
---
arch/x86/mm/pageattr.c | 29 +++++++++++++++++------------
1 file changed, 17 insertions(+), 12 deletions(-)
--- a/arch/x86/mm/pageattr.c
+++ b/arch/x86/mm/pageattr.c
@@ -251,15 +251,7 @@ static unsigned long __cpa_addr(struct c
* Flushing functions
*/
-/**
- * clflush_cache_range - flush a cache range with clflush
- * @vaddr: virtual start address
- * @size: number of bytes to flush
- *
- * clflushopt is an unordered instruction which needs fencing with mfence or
- * sfence to avoid ordering issues.
- */
-void clflush_cache_range(void *vaddr, unsigned int size)
+static void clflush_cache_range_opt(void *vaddr, unsigned int size)
{
const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
@@ -268,11 +260,22 @@ void clflush_cache_range(void *vaddr, un
if (p >= vend)
return;
- mb();
-
for (; p < vend; p += clflush_size)
clflushopt(p);
+}
+/**
+ * clflush_cache_range - flush a cache range with clflush
+ * @vaddr: virtual start address
+ * @size: number of bytes to flush
+ *
+ * clflushopt is an unordered instruction which needs fencing with mfence or
+ * sfence to avoid ordering issues.
+ */
+void clflush_cache_range(void *vaddr, unsigned int size)
+{
+ mb();
+ clflush_cache_range_opt(vaddr, size);
mb();
}
EXPORT_SYMBOL_GPL(clflush_cache_range);
@@ -339,6 +342,7 @@ static void cpa_flush(struct cpa_data *d
if (!cache)
return;
+ mb();
for (i = 0; i < cpa->numpages; i++) {
unsigned long addr = __cpa_addr(cpa, i);
unsigned int level;
@@ -349,8 +353,9 @@ static void cpa_flush(struct cpa_data *d
* Only flush present addresses:
*/
if (pte && (pte_val(*pte) & _PAGE_PRESENT))
- clflush_cache_range((void *)addr, PAGE_SIZE);
+ clflush_cache_range_opt((void *)addr, PAGE_SIZE);
}
+ mb();
}
static bool overlaps(unsigned long r1_start, unsigned long r1_end,
next prev parent reply other threads:[~2018-11-30 14:06 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-11-30 13:44 [PATCH 0/4] x86/mm/cpa: Fix cpa-array TLB invalidation Peter Zijlstra
2018-11-30 13:44 ` [PATCH 1/4] x86/mm/cpa: Add __cpa_addr() helper Peter Zijlstra
2018-11-30 13:44 ` [PATCH 2/4] x86/mm/cpa: Fix cpa_flush_array() Peter Zijlstra
2018-11-30 17:43 ` Dave Hansen
2018-11-30 13:44 ` [PATCH 3/4] x86/mm/cpa: Fold cpa_flush_range() and cpa_flush_array() Peter Zijlstra
2018-11-30 13:44 ` Peter Zijlstra [this message]
2018-11-30 14:52 ` [PATCH 0/4] x86/mm/cpa: Fix cpa-array TLB invalidation StDenis, Tom
[not found] ` <BN6PR12MB180942F2C841FD138A046569F7D30@BN6PR12MB1809.namprd12.prod.outlook.com>
2018-11-30 15:08 ` StDenis, Tom
2018-11-30 15:09 ` Peter Zijlstra
2018-11-30 15:10 ` StDenis, Tom
2018-11-30 15:14 ` StDenis, Tom
2018-11-30 15:23 ` Peter Zijlstra
2018-11-30 15:27 ` StDenis, Tom
2018-11-30 17:50 ` Peter Zijlstra
2018-11-30 15:31 ` Peter Zijlstra
2018-11-30 16:19 ` StDenis, Tom
2018-11-30 17:48 ` Peter Zijlstra
2018-11-30 17:49 ` StDenis, Tom
2018-11-30 18:06 ` Peter Zijlstra
2018-12-03 15:41 ` Peter Zijlstra
2018-12-03 19:26 ` StDenis, Tom
2018-12-05 16:24 ` StDenis, Tom
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