[3/3] ARM: dts: imx7ulp: add HSRUN mode clocks
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Message ID 1544176659-32022-3-git-send-email-Anson.Huang@nxp.com
State New
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Series
  • [1/3] dt-bindings: clock: imx7ulp: add HSRUN mode related clocks
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Commit Message

Anson Huang Dec. 7, 2018, 10:03 a.m. UTC
i.MX7ULP can switch CPU between RUN mode and HSRUN mode
by programming SMC1 register, different clock sources
will be used for CPU in different modes, so SMC1 can be
abstracted as a clock controller for CPU clock switch,
this patch adds support for it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
This patch is based on top of path series: [V5,1/6] dt-bindings: fsl: add compatible for imx7ulp evk,
https://patchwork.kernel.org/patch/10677263/
---
 arch/arm/boot/dts/imx7ulp.dtsi | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dtsi
index 931b275..b86daf7 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -199,9 +199,13 @@ 
 			assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
 		};
 
-		smc1: smc1@40410000 {
+		smc1: clock-controller@40410000 {
 			compatible = "fsl,imx7ulp-smc1";
 			reg = <0x40410000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&scg1 IMX7ULP_CLK_CORE_DIV>,
+				 <&scg1 IMX7ULP_CLK_HSRUN_CORE_DIV>;
+			clock-names = "divcore", "hsrun_divcore";
 		};
 
 		pcc3: clock-controller@40b30000 {