clk: qcom: Add missing msm8998 resets
diff mbox series

Message ID 1544558404-1705-1-git-send-email-jhugo@codeaurora.org
State Accepted
Commit a1697aba2721bebd5af2a041b9c251ce9bf7631e
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Series
  • clk: qcom: Add missing msm8998 resets
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Commit Message

Jeffrey Hugo Dec. 11, 2018, 8 p.m. UTC
commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
missed two USB2 resets.  Add them.

Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
---

Sorry, noticed this when working on USB.  I double checked the documentation
again, and I'm reasonably sure I got them all now.

 drivers/clk/qcom/gcc-msm8998.c               | 2 ++
 include/dt-bindings/clock/qcom,gcc-msm8998.h | 2 ++
 2 files changed, 4 insertions(+)

Comments

Stephen Boyd Dec. 11, 2018, 9:26 p.m. UTC | #1
Quoting Jeffrey Hugo (2018-12-11 12:00:04)
> commit c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
> missed two USB2 resets.  Add them.
> 
> Fixes: c0cb7c7e7164 ("clk: qcom: Enumerate remaining msm8998 resets")
> Signed-off-by: Jeffrey Hugo <jhugo@codeaurora.org>
> ---

Applied to clk-next

Patch
diff mbox series

diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 5f989ee..f3c2ab4 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -2827,6 +2827,8 @@  enum {
 	[GCC_MMSS_BCR] = { 0xb000 },
 	[GCC_QDSS_BCR] = { 0xc000 },
 	[GCC_WCSS_BCR] = { 0x11000 },
+	[GCC_QUSB2PHY_PRIM_BCR] = { 0x12000 },
+	[GCC_QUSB2PHY_SEC_BCR] = { 0x12004 },
 	[GCC_BLSP1_BCR] = { 0x17000 },
 	[GCC_BLSP1_UART1_BCR] = { 0x1a000 },
 	[GCC_BLSP1_UART2_BCR] = { 0x1c000 },
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8998.h b/include/dt-bindings/clock/qcom,gcc-msm8998.h
index 958fe83..ba84bba 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8998.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8998.h
@@ -296,5 +296,7 @@ 
 #define GCC_GLM_BCR						103
 #define GCC_SKL_BCR						104
 #define GCC_MSMPU_BCR						105
+#define GCC_QUSB2PHY_PRIM_BCR					106
+#define GCC_QUSB2PHY_SEC_BCR					107
 
 #endif