From: Paul Walmsley <paul.walmsley@sifive.com>
To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
devicetree@vger.kernel.org, Paul Walmsley <paul@pwsan.com>
Subject: [PATCH 4/7] dt-bindings: riscv: cpus: add U54 cores to the list of documented CPUs
Date: Fri, 14 Dec 2018 21:21:51 -0800 [thread overview]
Message-ID: <20181215052154.24347-5-paul.walmsley@sifive.com> (raw)
In-Reply-To: <20181215052154.24347-1-paul.walmsley@sifive.com>
Add compatible strings for the SiFive U54 family of CPU cores to the
RISC-V CPU compatible string documentation. The U54 CPU cores are
described in:
https://static.dev.sifive.com/FU540-C000-v1.0.pdf
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: devicetree@vger.kernel.org
Cc: linux-riscv@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
---
Documentation/devicetree/bindings/riscv/cpus.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.txt b/Documentation/devicetree/bindings/riscv/cpus.txt
index fb9d4f86f41f..d8d99b6b5386 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.txt
+++ b/Documentation/devicetree/bindings/riscv/cpus.txt
@@ -70,7 +70,8 @@ described below.
Value type: <stringlist>
Definition: must contain "riscv", may contain one or
more of "sifive,rocket0", "sifive,e51",
- "sifive,e5"
+ "sifive,e5", "sifive,u54-mc", "sifive,u54",
+ "sifive,u5"
- mmu-type:
Usage: optional
Value type: <string>
--
2.20.0
next prev parent reply other threads:[~2018-12-15 5:22 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-15 5:21 [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
2018-12-15 5:21 ` [PATCH 1/7] arch: riscv: add support for building DTB files from DT source data Paul Walmsley
2018-12-15 5:21 ` [PATCH 2/7] dt-bindings: riscv: sifive: add documentation for the SiFive FU540 Paul Walmsley
2018-12-20 20:57 ` Rob Herring
2018-12-15 5:21 ` [PATCH 3/7] dt-bindings: riscv: cpus: add E51 cores to the list of documented CPUs Paul Walmsley
2018-12-20 21:01 ` Rob Herring
2019-01-04 22:46 ` Palmer Dabbelt
2019-01-05 1:10 ` Rob Herring
2018-12-15 5:21 ` Paul Walmsley [this message]
2018-12-15 5:21 ` [PATCH 5/7] riscv: dts: add initial support for the SiFive FU540-C000 SoC Paul Walmsley
2018-12-16 3:12 ` kbuild test robot
2019-01-21 14:10 ` Johan Hovold
2018-12-15 5:21 ` [PATCH 6/7] dt-binding: riscv: sifive: add documentation for FU540-based boards Paul Walmsley
2018-12-20 21:04 ` Rob Herring
2018-12-15 5:21 ` [PATCH 7/7] riscv: dts: add initial board data for the SiFive HiFive Unleashed Paul Walmsley
2018-12-20 21:31 ` Rob Herring
2019-04-06 23:14 ` Paul Walmsley
2018-12-16 23:35 ` [PATCH 0/7] arch: riscv: add DT file support, starting with the SiFive HiFive-U Paul Walmsley
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