From: Sowjanya Komatineni <skomatineni@nvidia.com>
To: <robh+dt@kernel.org>, <mark.rutland@arm.com>,
<mperttunen@nvidia.com>, <thierry.reding@gmail.com>,
<jonathanh@nvidia.com>, <adrian.hunter@intel.com>,
<ulf.hansson@linaro.org>
Cc: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,
Sowjanya Komatineni <skomatineni@nvidia.com>
Subject: [PATCH V4 2/4] mmc: cqhci: DMA Configuration prior to CQE
Date: Wed, 19 Dec 2018 15:42:16 -0800 [thread overview]
Message-ID: <1545262938-20636-3-git-send-email-skomatineni@nvidia.com> (raw)
In-Reply-To: <1545262938-20636-1-git-send-email-skomatineni@nvidia.com>
eMMC-5.1 JESD84-B51 Spec (Section 6.6.39.1), mentions "Prior to
enabling command queuing, the block size shall be set to 512 B.
Device may respond with an error to CMD46/CMD47 if block size
is not 512 B".
This patch fixes the sequence to follow exact as per the spec.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
---
drivers/mmc/host/cqhci.c | 18 +++++++++++++++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/cqhci.c b/drivers/mmc/host/cqhci.c
index 159270e947cf..f701342e7212 100644
--- a/drivers/mmc/host/cqhci.c
+++ b/drivers/mmc/host/cqhci.c
@@ -248,6 +248,9 @@ static void __cqhci_enable(struct cqhci_host *cq_host)
cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
}
+ if (cq_host->ops->enable)
+ cq_host->ops->enable(mmc);
+
cqcfg &= ~(CQHCI_DCMD | CQHCI_TASK_DESC_SZ);
if (mmc->caps2 & MMC_CAP2_CQE_DCMD)
@@ -273,9 +276,6 @@ static void __cqhci_enable(struct cqhci_host *cq_host)
mmc->cqe_on = true;
- if (cq_host->ops->enable)
- cq_host->ops->enable(mmc);
-
/* Ensure all writes are done before interrupts are enabled */
wmb();
@@ -561,6 +561,7 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
int tag = cqhci_tag(mrq);
struct cqhci_host *cq_host = mmc->cqe_private;
unsigned long flags;
+ u32 cqcfg = 0;
if (!cq_host->enabled) {
pr_err("%s: cqhci: not enabled\n", mmc_hostname(mmc));
@@ -579,8 +580,19 @@ static int cqhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
pr_err("%s: cqhci: CQE failed to exit halt state\n",
mmc_hostname(mmc));
}
+ /* Configuration must not be changed while enabled */
+ cqcfg = cqhci_readl(cq_host, CQHCI_CFG);
+ if (cqcfg & CQHCI_ENABLE) {
+ cqcfg &= ~CQHCI_ENABLE;
+ cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
+ }
+
if (cq_host->ops->enable)
cq_host->ops->enable(mmc);
+
+ cqcfg |= CQHCI_ENABLE;
+ cqhci_writel(cq_host, cqcfg, CQHCI_CFG);
+
}
if (mrq->data) {
--
2.7.4
next prev parent reply other threads:[~2018-12-19 23:42 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-19 23:42 [PATCH V4 0/4] HW Command Queue support for Tegra SDMMC Sowjanya Komatineni
2018-12-19 23:42 ` [PATCH V4 1/4] mmc: sdhci: Fix sdhci_do_enable_v4_mode Sowjanya Komatineni
2018-12-19 23:42 ` Sowjanya Komatineni [this message]
2018-12-20 12:37 ` [PATCH V4 2/4] mmc: cqhci: DMA Configuration prior to CQE Adrian Hunter
2018-12-20 21:01 ` Sowjanya Komatineni
2018-12-21 7:41 ` Adrian Hunter
2018-12-19 23:42 ` [PATCH V4 3/4] arm64: dtsi: Fix SDMMC address range Sowjanya Komatineni
2018-12-19 23:42 ` [PATCH V4 4/4] mmc: tegra: HW Command Queue Support for Tegra SDMMC Sowjanya Komatineni
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