From: Andrey Smirnov <andrew.smirnov@gmail.com>
To: linux-pci@vger.kernel.org
Cc: Andrey Smirnov <andrew.smirnov@gmail.com>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Fabio Estevam <fabio.estevam@nxp.com>,
Chris Healy <cphealy@gmail.com>,
Lucas Stach <l.stach@pengutronix.de>,
Leonard Crestez <leonard.crestez@nxp.com>,
"A.s. Dong" <aisheng.dong@nxp.com>,
Richard Zhu <hongxing.zhu@nxp.com>,
linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 08/21] PCI: designware: Share code for dw_pcie_rd/wr_other_conf()
Date: Thu, 20 Dec 2018 23:27:03 -0800 [thread overview]
Message-ID: <20181221072716.29017-9-andrew.smirnov@gmail.com> (raw)
In-Reply-To: <20181221072716.29017-1-andrew.smirnov@gmail.com>
Default implementation of pcie_rd_other_conf() and
dw_pcie_wd_other_conf() share more than 80% of their code. Move shared
code into a dedicated subroutine and convert pcie_rd_other_conf() and
dw_pcie_wd_other_conf() to use it. No functional change intended.
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Chris Healy <cphealy@gmail.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-pci@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
.../pci/controller/dwc/pcie-designware-host.c | 61 +++++++------------
1 file changed, 23 insertions(+), 38 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 721d60a5d9e4..8f957cd6901b 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -512,8 +512,9 @@ int dw_pcie_host_init(struct pcie_port *pp)
return ret;
}
-static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
- u32 devfn, int where, int size, u32 *val)
+static int dw_pcie_access_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val,
+ bool write)
{
int ret, type;
u32 busdev, cfg_size;
@@ -521,9 +522,6 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
void __iomem *va_cfg_base;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
- if (pp->ops->rd_other_conf)
- return pp->ops->rd_other_conf(pp, bus, devfn, where, size, val);
-
busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
PCIE_ATU_FUNC(PCI_FUNC(devfn));
@@ -542,7 +540,11 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
type, cpu_addr,
busdev, cfg_size);
- ret = dw_pcie_read(va_cfg_base + where, size, val);
+ if (write)
+ ret = dw_pcie_write(va_cfg_base + where, size, *val);
+ else
+ ret = dw_pcie_read(va_cfg_base + where, size, val);
+
if (pci->num_viewport <= 2)
dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
PCIE_ATU_TYPE_IO, pp->io_base,
@@ -551,43 +553,26 @@ static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
return ret;
}
+static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
+ u32 devfn, int where, int size, u32 *val)
+{
+ if (pp->ops->rd_other_conf)
+ return pp->ops->rd_other_conf(pp, bus, devfn, where,
+ size, val);
+
+ return dw_pcie_access_other_conf(pp, bus, devfn, where, size, val,
+ false);
+}
+
static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
u32 devfn, int where, int size, u32 val)
{
- int ret, type;
- u32 busdev, cfg_size;
- u64 cpu_addr;
- void __iomem *va_cfg_base;
- struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-
if (pp->ops->wr_other_conf)
- return pp->ops->wr_other_conf(pp, bus, devfn, where, size, val);
-
- busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
- PCIE_ATU_FUNC(PCI_FUNC(devfn));
+ return pp->ops->wr_other_conf(pp, bus, devfn, where,
+ size, val);
- if (bus->parent->number == pp->root_bus_nr) {
- type = PCIE_ATU_TYPE_CFG0;
- cpu_addr = pp->cfg0_base;
- cfg_size = pp->cfg0_size;
- va_cfg_base = pp->va_cfg0_base;
- } else {
- type = PCIE_ATU_TYPE_CFG1;
- cpu_addr = pp->cfg1_base;
- cfg_size = pp->cfg1_size;
- va_cfg_base = pp->va_cfg1_base;
- }
-
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
- type, cpu_addr,
- busdev, cfg_size);
- ret = dw_pcie_write(va_cfg_base + where, size, val);
- if (pci->num_viewport <= 2)
- dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX1,
- PCIE_ATU_TYPE_IO, pp->io_base,
- pp->io_bus_addr, pp->io_size);
-
- return ret;
+ return dw_pcie_access_other_conf(pp, bus, devfn, where, size, &val,
+ true);
}
static int dw_pcie_valid_device(struct pcie_port *pp, struct pci_bus *bus,
--
2.19.1
next prev parent reply other threads:[~2018-12-21 7:27 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-21 7:26 [PATCH 00/21] i.MX6, DesignWare PCI improvements Andrey Smirnov
2018-12-21 7:26 ` [PATCH 01/21] PCI: imx6: Simplify imx7d_pcie_wait_for_phy_pll_lock() Andrey Smirnov
2018-12-21 7:26 ` [PATCH 02/21] PCI: imx6: Remove redundant debug tracing Andrey Smirnov
2018-12-21 7:26 ` [PATCH 03/21] PCI: imx6: Return -ETIMEOUT from imx6_pcie_wait_for_speed_change() Andrey Smirnov
2018-12-21 7:26 ` [PATCH 04/21] PCI: imx6: Remove duplicate macro definitions Andrey Smirnov
2018-12-21 7:27 ` [PATCH 05/21] PCI: imx6: Remove PCIE_PL_PFLR_* constants Andrey Smirnov
2018-12-21 7:27 ` [PATCH 06/21] PCI: imx6: Remove PCIE_PHY_RX_ASIC_OUT* constants Andrey Smirnov
2018-12-21 7:27 ` [PATCH 07/21] PCI: designware: Make use of IS_ALIGNED() Andrey Smirnov
2019-01-02 9:33 ` Gustavo Pimentel
2019-01-04 18:37 ` Joe Perches
2019-01-04 18:52 ` Andrey Smirnov
2018-12-21 7:27 ` Andrey Smirnov [this message]
2019-01-02 10:21 ` [PATCH 08/21] PCI: designware: Share code for dw_pcie_rd/wr_other_conf() Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 09/21] PCI: imx6: Drop imx6_pcie_link_up() Andrey Smirnov
2018-12-21 18:55 ` Trent Piepho
2018-12-22 0:39 ` Andrey Smirnov
2018-12-21 7:27 ` [PATCH 10/21] PCI: designware: imx6: Share PHY debug register definitions Andrey Smirnov
2018-12-21 7:27 ` [PATCH 11/21] PCI: designware: Make use of BIT() in constant definitions Andrey Smirnov
2018-12-26 15:14 ` Gustavo Pimentel
2019-01-02 18:28 ` Andrey Smirnov
2019-01-02 18:31 ` Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 12/21] PCI: imx6: " Andrey Smirnov
2018-12-21 7:27 ` [PATCH 13/21] PCI: imx6: Simplify bit operations in PHY functions Andrey Smirnov
2018-12-21 7:27 ` [PATCH 14/21] PCI: imx6: Simplify pcie_phy_poll_ack() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 15/21] PCI: imx6: Restrict PHY register data to 16-bit Andrey Smirnov
2018-12-21 7:27 ` [PATCH 16/21] PCI: imx6: Pass data to dw_pcie_writel_dbi() directly Andrey Smirnov
2018-12-21 7:27 ` [PATCH 17/21] PCI: imx6: Use common mask in imx6_pcie_reset_phy() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 18/21] PCI: imx6: Simplify bit operations in imx6_setup_phy_mpll() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 19/21] PCI: imx6: Remove magic numbers from imx6_pcie_establish_link() Andrey Smirnov
2018-12-21 7:27 ` [PATCH 20/21] PCI: designware: Make use of GENMASK/FIELD_PREP Andrey Smirnov
2018-12-26 15:07 ` Gustavo Pimentel
2018-12-21 7:27 ` [PATCH 21/21] PCI: designware: Remove superfluous shifting in definitions Andrey Smirnov
2018-12-26 14:49 ` Gustavo Pimentel
2018-12-26 15:26 ` [PATCH 00/21] i.MX6, DesignWare PCI improvements Gustavo Pimentel
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