From: <Oliver.Rohe@wago.com>
To: <a.zummo@towertech.it>, <alexandre.belloni@bootlin.com>
Cc: <linux-rtc@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<Oliver.Rohe@wago.com>
Subject: [PATCH] rtc: rs5c372: r2221: fix to use the correct XSTP bit
Date: Wed, 9 Jan 2019 10:59:40 +0000 [thread overview]
Message-ID: <1547031572-7097-1-git-send-email-oliver.rohe@wago.com> (raw)
The Ricoh chips have slightly different register layouts
and the r2221 chip uses bit 5 as the oscillator halt sensor bit.
Signed-off-by: Olive Rohe <oliver.rohe@wago.com>
---
drivers/rtc/rtc-rs5c372.c | 32 +++++++++++++++++++++-----------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/rtc/rtc-rs5c372.c b/drivers/rtc/rtc-rs5c372.c
index c503832..ff35dce 100644
--- a/drivers/rtc/rtc-rs5c372.c
+++ b/drivers/rtc/rtc-rs5c372.c
@@ -52,8 +52,8 @@
# define RS5C_CTRL1_CT4 (4 << 0) /* 1 Hz level irq */
#define RS5C_REG_CTRL2 15
# define RS5C372_CTRL2_24 (1 << 5)
-# define R2025_CTRL2_XST (1 << 5)
-# define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2025S/D */
+# define R2x2x_CTRL2_XSTP (1 << 5) /* only if R2x2x */
+# define RS5C_CTRL2_XSTP (1 << 4) /* only if !R2x2x */
# define RS5C_CTRL2_CTFG (1 << 2)
# define RS5C_CTRL2_AAFG (1 << 1) /* or WAFG */
# define RS5C_CTRL2_BAFG (1 << 0) /* or DAFG */
@@ -519,20 +519,30 @@ static int rs5c_oscillator_setup(struct rs5c372 *rs5c372)
unsigned char buf[2];
int addr, i, ret = 0;
- if (rs5c372->type == rtc_r2025sd) {
- if (rs5c372->regs[RS5C_REG_CTRL2] & R2025_CTRL2_XST)
+ addr = RS5C_ADDR(RS5C_REG_CTRL1);
+ buf[0] = rs5c372->regs[RS5C_REG_CTRL1];
+ buf[1] = rs5c372->regs[RS5C_REG_CTRL2];
+
+ /* handle xstp bit */
+ switch (rs5c372->type) {
+ case rtc_r2025sd:
+ if (buf[1] & R2x2x_CTRL2_XSTP)
return ret;
- rs5c372->regs[RS5C_REG_CTRL2] |= R2025_CTRL2_XST;
- } else {
- if (!(rs5c372->regs[RS5C_REG_CTRL2] & RS5C_CTRL2_XSTP))
+ rs5c372->regs[RS5C_REG_CTRL2] |= R2x2x_CTRL2_XSTP;
+ break;
+ case rtc_r2221tl:
+ if (!(buf[1] & R2x2x_CTRL2_XSTP))
+ return ret;
+ rs5c372->regs[RS5C_REG_CTRL2] &= ~R2x2x_CTRL2_XSTP;
+ break;
+
+ default:
+ if (!(buf[1] & RS5C_CTRL2_XSTP))
return ret;
rs5c372->regs[RS5C_REG_CTRL2] &= ~RS5C_CTRL2_XSTP;
+ break;
}
- addr = RS5C_ADDR(RS5C_REG_CTRL1);
- buf[0] = rs5c372->regs[RS5C_REG_CTRL1];
- buf[1] = rs5c372->regs[RS5C_REG_CTRL2];
-
/* use 24hr mode */
switch (rs5c372->type) {
case rtc_rs5c372a:
--
2.7.4
next reply other threads:[~2019-01-09 10:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-09 10:59 Oliver.Rohe [this message]
2019-01-11 10:05 ` [PATCH] rtc: rs5c372: r2221: fix to use the correct XSTP bit Alexandre Belloni
2019-01-11 10:39 ` Oliver.Rohe
2019-02-05 21:57 ` Alexandre Belloni
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