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From: Maxime Chevallier <maxime.chevallier@bootlin.com>
To: davem@davemloft.net
Cc: Maxime Chevallier <maxime.chevallier@bootlin.com>,
	netdev@vger.kernel.org, linux-kernel@vger.kernel.org,
	Andrew Lunn <andrew@lunn.ch>,
	Florian Fainelli <f.fainelli@gmail.com>,
	Heiner Kallweit <hkallweit1@gmail.com>,
	Russell King <linux@armlinux.org.uk>,
	linux-arm-kernel@lists.infradead.org,
	Antoine Tenart <antoine.tenart@bootlin.com>,
	thomas.petazzoni@bootlin.com, gregory.clement@bootlin.com,
	miquel.raynal@bootlin.com, nadavh@marvell.com,
	stefanc@marvell.com, mw@semihalf.com
Subject: [PATCH net-next 4/7] net: phy: marvell10g: Add support for 2.5GBASET and 5GBASET
Date: Fri, 18 Jan 2019 16:23:49 +0100	[thread overview]
Message-ID: <20190118152352.26417-5-maxime.chevallier@bootlin.com> (raw)
In-Reply-To: <20190118152352.26417-1-maxime.chevallier@bootlin.com>

The Marvell Alaska family of PHYs supports 2.5GBaseT and 5GBaseT modes,
as defined in the 802.3bz specification.

When the link partner requests a 2.5GBASET link, the PHY will
reconfigure it's MII interface to 2500BASEX.

At 5G, the PHY will reconfigure it's interface to 5GBASE-R, but this
mode isn't supported by any MAC for now.

This was tested with :
 - The 88X3310, which is on the MacchiatoBin
 - The 88E2010, an Alaska PHY that has no fiber interfaces, and is
   limited to 5G maximum speed.

Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
 drivers/net/phy/marvell10g.c | 31 +++++++++++++++++++++++--------
 1 file changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/net/phy/marvell10g.c b/drivers/net/phy/marvell10g.c
index f2a6d6e7041a..f45ddf3bc138 100644
--- a/drivers/net/phy/marvell10g.c
+++ b/drivers/net/phy/marvell10g.c
@@ -255,6 +255,7 @@ static int mv3310_config_init(struct phy_device *phydev)
 
 	/* Check that the PHY interface type is compatible */
 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
 	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
 	    phydev->interface != PHY_INTERFACE_MODE_RXAUI &&
 	    phydev->interface != PHY_INTERFACE_MODE_10GKR)
@@ -264,8 +265,10 @@ static int mv3310_config_init(struct phy_device *phydev)
 	if (ret)
 		return ret;
 
-	linkmode_and(phydev->advertising, phydev->advertising,
-		     phydev->supported);
+	/* Make sure we advertise all the supported modes, and not just the
+	 * default one specified in the driver's .features.
+	 */
+	linkmode_copy(phydev->advertising, phydev->supported);
 
 	return 0;
 }
@@ -314,8 +317,17 @@ static int mv3310_config_aneg(struct phy_device *phydev)
 	else
 		reg = 0;
 
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+			      phydev->advertising))
+		reg |= MDIO_AN_10GBT_CTRL_ADV2_5G;
+	if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+			      phydev->advertising))
+		reg |= MDIO_AN_10GBT_CTRL_ADV5G;
+
 	ret = mv3310_modify(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
-			    MDIO_AN_10GBT_CTRL_ADV10G, reg);
+			    MDIO_AN_10GBT_CTRL_ADV10G |
+			    MDIO_AN_10GBT_CTRL_ADV5G |
+			    MDIO_AN_10GBT_CTRL_ADV2_5G, reg);
 	if (ret < 0)
 		return ret;
 	if (ret > 0)
@@ -344,17 +356,20 @@ static int mv3310_aneg_done(struct phy_device *phydev)
 static void mv3310_update_interface(struct phy_device *phydev)
 {
 	if ((phydev->interface == PHY_INTERFACE_MODE_SGMII ||
+	     phydev->interface == PHY_INTERFACE_MODE_2500BASEX ||
 	     phydev->interface == PHY_INTERFACE_MODE_10GKR) && phydev->link) {
 		/* The PHY automatically switches its serdes interface (and
-		 * active PHYXS instance) between Cisco SGMII and 10GBase-KR
-		 * modes according to the speed.  Florian suggests setting
-		 * phydev->interface to communicate this to the MAC. Only do
-		 * this if we are already in either SGMII or 10GBase-KR mode.
+		 * active PHYXS instance) between Cisco SGMII, 10GBase-KR and
+		 * 2500BaseX modes according to the speed.  Florian suggests
+		 * setting phydev->interface to communicate this to the MAC.
+		 * Only do this if we are already in one of the above modes.
 		 */
 		if (phydev->speed == SPEED_10000)
 			phydev->interface = PHY_INTERFACE_MODE_10GKR;
+		else if (phydev->speed == SPEED_2500)
+			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
 		else if (phydev->speed >= SPEED_10 &&
-			 phydev->speed < SPEED_10000)
+			 phydev->speed < SPEED_2500)
 			phydev->interface = PHY_INTERFACE_MODE_SGMII;
 	}
 }
-- 
2.19.2


  parent reply	other threads:[~2019-01-18 15:24 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-18 15:23 [PATCH net-next 0/7] net: phy: Add support for 2.5GBASET PHYs Maxime Chevallier
2019-01-18 15:23 ` [PATCH net-next 1/7] net: phy: Extract genphy_c45_read_abilities from marvell10g Maxime Chevallier
2019-01-20 18:51   ` Andrew Lunn
2019-01-21 16:20     ` Maxime Chevallier
2019-01-21 16:28       ` Andrew Lunn
2019-01-18 15:23 ` [PATCH net-next 2/7] net: phy: Add generic support for 2.5GBaseT and 5GBaseT Maxime Chevallier
2019-01-18 15:23 ` [PATCH net-next 3/7] net: phy: Read 2.5G and 5G extended abilities Maxime Chevallier
2019-01-18 15:23 ` Maxime Chevallier [this message]
2019-01-18 15:51   ` [PATCH net-next 4/7] net: phy: marvell10g: Add support for 2.5GBASET and 5GBASET Russell King - ARM Linux admin
2019-01-21 20:17   ` Andrew Lunn
2019-01-22 10:08     ` Maxime Chevallier
2019-01-18 15:23 ` [PATCH net-next 5/7] net: phy: marvell10g: Force reading of 2.5/5G PMA extended abilities Maxime Chevallier
2019-01-20 19:08   ` Andrew Lunn
2019-01-21 10:35     ` Maxime Chevallier
2019-01-21 10:52       ` Russell King - ARM Linux admin
2019-01-21 12:29         ` Maxime Chevallier
2019-01-21 13:00           ` Russell King - ARM Linux admin
2019-01-28 14:26             ` Maxime Chevallier
2019-02-07 23:37               ` Russell King - ARM Linux admin
2019-01-18 15:23 ` [PATCH net-next 6/7] net: mvpp2: Add 2.5GBaseT support Maxime Chevallier
2019-01-18 15:23 ` [PATCH net-next 7/7] net: phy: marvell10g: add support for the 88x2110 PHY Maxime Chevallier
2019-01-20 19:10   ` Andrew Lunn

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