From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org
Cc: b.zolnierkie@samsung.com, myungjoo.ham@samsung.com,
krzk@kernel.org, Lukasz Luba <l.luba@partner.samsung.com>,
Sylwester Nawrocki <s.nawrocki@samsung.com>,
Chanwoo Choi <cw00.choi@samsung.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Kukjin Kim <kgene@kernel.org>,
linux-samsung-soc@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420
Date: Mon, 28 Jan 2019 20:21:32 +0100 [thread overview]
Message-ID: <1548703299-15806-2-git-send-email-l.luba@partner.samsung.com> (raw)
In-Reply-To: <1548703299-15806-1-git-send-email-l.luba@partner.samsung.com>
Define new IDs for clocks used by Dynamic Memory Controller in
Exynos5422 SoC.
CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Chanwoo Choi <cw00.choi@samsung.com>
CC: Rob Herring <robh+dt@kernel.org>
CC: Mark Rutland <mark.rutland@arm.com>
CC: Kukjin Kim <kgene@kernel.org>
CC: Krzysztof Kozlowski <krzk@kernel.org>
CC: linux-samsung-soc@vger.kernel.org
CC: devicetree@vger.kernel.org
CC: linux-arm-kernel@lists.infradead.org
CC: linux-kernel@vger.kernel.org
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 355f469..1827a64 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -60,6 +60,7 @@
#define CLK_MAU_EPLL 159
#define CLK_SCLK_HSIC_12M 160
#define CLK_SCLK_MPHY_IXTAL24 161
+#define CLK_SCLK_BPLL 162
/* gate clocks */
#define CLK_UART0 257
@@ -195,6 +196,16 @@
#define CLK_ACLK432_CAM 518
#define CLK_ACLK_FL1550_CAM 519
#define CLK_ACLK550_CAM 520
+#define CLK_CLKM_PHY0 521
+#define CLK_CLKM_PHY1 522
+#define CLK_ACLK_PPMU_DREX0_0 523
+#define CLK_ACLK_PPMU_DREX0_1 524
+#define CLK_ACLK_PPMU_DREX1_0 525
+#define CLK_ACLK_PPMU_DREX1_1 526
+#define CLK_PCLK_PPMU_DREX0_0 527
+#define CLK_PCLK_PPMU_DREX0_1 528
+#define CLK_PCLK_PPMU_DREX1_0 529
+#define CLK_PCLK_PPMU_DREX1_1 530
/* mux clocks */
#define CLK_MOUT_HDMI 640
@@ -217,6 +228,10 @@
#define CLK_MOUT_EPLL 657
#define CLK_MOUT_MAU_EPLL 658
#define CLK_MOUT_USER_MAU_EPLL 659
+#define CLK_MOUT_DPLL 660
+#define CLK_MOUT_ACLK_G3D 661
+#define CLK_MOUT_SCLK_SPLL 662
+#define CLK_MOUT_MX_MSPLL_CCORE_PHY 663
/* divider clocks */
#define CLK_DOUT_PIXEL 768
@@ -248,8 +263,9 @@
#define CLK_DOUT_CCLK_DREX0 794
#define CLK_DOUT_CLK2X_PHY0 795
#define CLK_DOUT_PCLK_CORE_MEM 796
+#define CLK_FF_DOUT_SPLL2 797
/* must be greater than maximal clock id */
-#define CLK_NR_CLKS 797
+#define CLK_NR_CLKS 798
#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
--
2.7.4
next parent reply other threads:[~2019-01-28 19:21 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <1548703299-15806-1-git-send-email-l.luba@partner.samsung.com>
[not found] ` <CGME20190128192151eucas1p1754d1286ff0f46e8e98796d7583d8e96@eucas1p1.samsung.com>
2019-01-28 19:21 ` Lukasz Luba [this message]
2019-01-29 0:54 ` [PATCH 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Chanwoo Choi
2019-01-29 15:57 ` Lukasz Luba
[not found] ` <CGME20190128192151eucas1p1d5ad3a851ffc8b56a7a62febdb6d5677@eucas1p1.samsung.com>
2019-01-28 19:21 ` [PATCH 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
[not found] ` <CGME20190128192152eucas1p118c23cce7c1f6d9a961cba8ae8304318@eucas1p1.samsung.com>
2019-01-28 19:21 ` [PATCH 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
[not found] ` <CGME20190128192153eucas1p2d7a796cb89e68c1789069562e91296be@eucas1p2.samsung.com>
2019-01-28 19:21 ` [PATCH 4/8] dt-bindings: devfreq: add DMC device description Lukasz Luba
2019-01-29 14:47 ` Krzysztof Kozlowski
2019-01-29 16:02 ` Lukasz Luba
2019-02-25 13:49 ` Rob Herring
[not found] ` <CGME20190128192153eucas1p14ea8461ed8f9d94955f2ff4fb3c4c790@eucas1p1.samsung.com>
2019-01-28 19:21 ` [PATCH 5/8] drivers: devfreq: exynos5: add DMC driver Lukasz Luba
2019-01-29 15:03 ` Krzysztof Kozlowski
2019-01-29 16:24 ` Lukasz Luba
[not found] ` <CGME20190128192154eucas1p2e696de47c5aab0cdb80cff32254daaf9@eucas1p2.samsung.com>
2019-01-28 19:21 ` [PATCH 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba
2019-01-29 15:13 ` Krzysztof Kozlowski
2019-01-29 17:06 ` Lukasz Luba
[not found] ` <CGME20190128192154eucas1p2719b339d9dd0d11468fd8e8ab171e84e@eucas1p2.samsung.com>
2019-01-28 19:21 ` [PATCH 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190128192155eucas1p13fa8616c0da161cd2f041ba241dba3d5@eucas1p1.samsung.com>
2019-01-28 19:21 ` [PATCH 8/8] arm: config: exynos: enable DMC driver Lukasz Luba
2019-01-29 15:15 ` Krzysztof Kozlowski
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