From: Julien Thierry <julien.thierry@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, daniel.thompson@linaro.org,
joel@joelfernandes.org, marc.zyngier@arm.com,
christoffer.dall@arm.com, james.morse@arm.com,
catalin.marinas@arm.com, will.deacon@arm.com,
mark.rutland@arm.com, Julien Thierry <julien.thierry@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>
Subject: [PATCH v10 16/25] irqchip/gic-v3: Factor group0 detection into functions
Date: Thu, 31 Jan 2019 14:58:54 +0000 [thread overview]
Message-ID: <1548946743-38979-17-git-send-email-julien.thierry@arm.com> (raw)
In-Reply-To: <1548946743-38979-1-git-send-email-julien.thierry@arm.com>
The code to detect whether Linux has access to group0 interrupts can
prove useful in other parts of the driver.
Provide a separate function to do this.
Signed-off-by: Julien Thierry <julien.thierry@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
---
drivers/irqchip/irq-gic-v3.c | 55 +++++++++++++++++++++++++++++---------------
1 file changed, 36 insertions(+), 19 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
index 8148a92..da547e0 100644
--- a/drivers/irqchip/irq-gic-v3.c
+++ b/drivers/irqchip/irq-gic-v3.c
@@ -400,6 +400,39 @@ static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs
}
}
+static u32 gic_get_pribits(void)
+{
+ u32 pribits;
+
+ pribits = gic_read_ctlr();
+ pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
+ pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
+ pribits++;
+
+ return pribits;
+}
+
+static bool gic_has_group0(void)
+{
+ u32 val;
+
+ /*
+ * Let's find out if Group0 is under control of EL3 or not by
+ * setting the highest possible, non-zero priority in PMR.
+ *
+ * If SCR_EL3.FIQ is set, the priority gets shifted down in
+ * order for the CPU interface to set bit 7, and keep the
+ * actual priority in the non-secure range. In the process, it
+ * looses the least significant bit and the actual priority
+ * becomes 0x80. Reading it back returns 0, indicating that
+ * we're don't have access to Group0.
+ */
+ gic_write_pmr(BIT(8 - gic_get_pribits()));
+ val = gic_read_pmr();
+
+ return val != 0;
+}
+
static void __init gic_dist_init(void)
{
unsigned int i;
@@ -541,7 +574,7 @@ static void gic_cpu_sys_reg_init(void)
u64 mpidr = cpu_logical_map(cpu);
u64 need_rss = MPIDR_RS(mpidr);
bool group0;
- u32 val, pribits;
+ u32 pribits;
/*
* Need to check that the SRE bit has actually been set. If
@@ -553,25 +586,9 @@ static void gic_cpu_sys_reg_init(void)
if (!gic_enable_sre())
pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n");
- pribits = gic_read_ctlr();
- pribits &= ICC_CTLR_EL1_PRI_BITS_MASK;
- pribits >>= ICC_CTLR_EL1_PRI_BITS_SHIFT;
- pribits++;
+ pribits = gic_get_pribits();
- /*
- * Let's find out if Group0 is under control of EL3 or not by
- * setting the highest possible, non-zero priority in PMR.
- *
- * If SCR_EL3.FIQ is set, the priority gets shifted down in
- * order for the CPU interface to set bit 7, and keep the
- * actual priority in the non-secure range. In the process, it
- * looses the least significant bit and the actual priority
- * becomes 0x80. Reading it back returns 0, indicating that
- * we're don't have access to Group0.
- */
- write_gicreg(BIT(8 - pribits), ICC_PMR_EL1);
- val = read_gicreg(ICC_PMR_EL1);
- group0 = val != 0;
+ group0 = gic_has_group0();
/* Set priority mask register */
write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
--
1.9.1
next prev parent reply other threads:[~2019-01-31 14:59 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 14:58 [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Julien Thierry
2019-01-31 14:58 ` [PATCH v10 01/25] arm64: Fix HCR.TGE status for NMI contexts Julien Thierry
2019-01-31 14:58 ` [PATCH v10 02/25] arm64: Remove unused daif related functions/macros Julien Thierry
2019-01-31 14:58 ` [PATCH v10 03/25] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature Julien Thierry
2019-01-31 14:58 ` [PATCH v10 04/25] arm64: cpufeature: Add cpufeature for IRQ priority masking Julien Thierry
2019-01-31 14:58 ` [PATCH v10 05/25] arm/arm64: gic-v3: Add PMR and RPR accessors Julien Thierry
2019-01-31 14:58 ` [PATCH v10 06/25] irqchip/gic-v3: Switch to PMR masking before calling IRQ handler Julien Thierry
2019-01-31 14:58 ` [PATCH v10 07/25] arm64: ptrace: Provide definitions for PMR values Julien Thierry
2019-01-31 14:58 ` [PATCH v10 08/25] arm64: Make PMR part of task context Julien Thierry
2019-01-31 14:58 ` [PATCH v10 09/25] arm64: Unmask PMR before going idle Julien Thierry
2019-01-31 14:58 ` [PATCH v10 10/25] arm64: kvm: Unmask PMR before entering guest Julien Thierry
2019-01-31 14:58 ` [PATCH v10 11/25] efi: Let architectures decide the flags that should be saved/restored Julien Thierry
2019-01-31 14:58 ` [PATCH v10 12/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking Julien Thierry
2019-02-08 4:35 ` Nathan Chancellor
2019-02-08 9:36 ` Julien Thierry
2019-02-08 16:00 ` Nathan Chancellor
2019-02-08 16:16 ` Catalin Marinas
2019-01-31 14:58 ` [PATCH v10 13/25] arm64: daifflags: Include PMR in daifflags restore operations Julien Thierry
2019-01-31 14:58 ` [PATCH v10 14/25] arm64: alternative: Allow alternative status checking per cpufeature Julien Thierry
2019-01-31 14:58 ` [PATCH v10 15/25] arm64: alternative: Apply alternatives early in boot process Julien Thierry
2019-01-31 14:58 ` Julien Thierry [this message]
2019-01-31 14:58 ` [PATCH v10 17/25] arm64: Switch to PMR masking when starting CPUs Julien Thierry
2019-01-31 14:58 ` [PATCH v10 18/25] arm64: gic-v3: Implement arch support for priority masking Julien Thierry
2019-01-31 14:58 ` [PATCH v10 19/25] irqchip/gic-v3: Detect if GIC can support pseudo-NMIs Julien Thierry
2019-01-31 14:58 ` [PATCH v10 20/25] irqchip/gic-v3: Handle pseudo-NMIs Julien Thierry
2019-01-31 14:58 ` [PATCH v10 21/25] irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI Julien Thierry
2019-01-31 14:59 ` [PATCH v10 22/25] arm64: Handle serror in NMI context Julien Thierry
2019-01-31 14:59 ` [PATCH v10 23/25] arm64: Skip preemption when exiting an NMI Julien Thierry
2019-01-31 14:59 ` [PATCH v10 24/25] arm64: Skip irqflags tracing for NMI in IRQs disabled context Julien Thierry
2019-01-31 14:59 ` [PATCH v10 25/25] arm64: Enable the support of pseudo-NMIs Julien Thierry
2019-02-06 10:27 ` [PATCH v10 00/25] arm64: provide pseudo NMI with GICv3 Catalin Marinas
2019-02-07 14:21 ` Daniel Thompson
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