From: Wei Wang <wei.w.wang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
pbonzini@redhat.com, ak@linux.intel.com, peterz@infradead.org
Cc: kan.liang@intel.com, mingo@redhat.com, rkrcmar@redhat.com,
like.xu@intel.com, wei.w.wang@intel.com, jannh@google.com,
arei.gonglei@huawei.com, jmattson@google.com
Subject: [PATCH v5 06/12] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest
Date: Thu, 14 Feb 2019 17:06:08 +0800 [thread overview]
Message-ID: <1550135174-5423-7-git-send-email-wei.w.wang@intel.com> (raw)
In-Reply-To: <1550135174-5423-1-git-send-email-wei.w.wang@intel.com>
Bits [0, 5] of MSR_IA32_PERF_CAPABILITIES tell about the format of
the addresses stored in the LBR stack. Expose those bits to the guest
when the guest lbr feature is enabled.
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Andi Kleen <ak@linux.intel.com>
---
arch/x86/include/asm/perf_event.h | 2 ++
arch/x86/kvm/cpuid.c | 2 +-
arch/x86/kvm/vmx/pmu_intel.c | 16 ++++++++++++++++
3 files changed, 19 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 2f82795..eee09b7 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -87,6 +87,8 @@
#define ARCH_PERFMON_BRANCH_MISSES_RETIRED 6
#define ARCH_PERFMON_EVENTS_COUNT 7
+#define X86_PERF_CAP_MASK_LBR_FMT 0x3f
+
/*
* Intel "Architectural Performance Monitoring" CPUID
* detection/enumeration details:
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index bbffa6c..708df80 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -363,7 +363,7 @@ static inline int __do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ |
0 /* DS-CPL, VMX, SMX, EST */ |
0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
- F(FMA) | F(CX16) | 0 /* xTPR Update, PDCM */ |
+ F(FMA) | F(CX16) | 0 /* xTPR Update*/ | F(PDCM) |
F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) |
F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) |
0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) |
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index cd3b5d2..cbc6015 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -153,6 +153,7 @@ static bool intel_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr)
case MSR_CORE_PERF_GLOBAL_STATUS:
case MSR_CORE_PERF_GLOBAL_CTRL:
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
+ case MSR_IA32_PERF_CAPABILITIES:
ret = pmu->version > 1;
break;
default:
@@ -318,6 +319,19 @@ static int intel_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
case MSR_CORE_PERF_GLOBAL_OVF_CTRL:
msr_info->data = pmu->global_ovf_ctrl;
return 0;
+ case MSR_IA32_PERF_CAPABILITIES: {
+ u64 data;
+
+ if (!boot_cpu_has(X86_FEATURE_PDCM) ||
+ (!msr_info->host_initiated &&
+ !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)))
+ return 1;
+ data = native_read_msr(MSR_IA32_PERF_CAPABILITIES);
+ msr_info->data = 0;
+ if (vcpu->kvm->arch.lbr_in_guest)
+ msr_info->data |= (data & X86_PERF_CAP_MASK_LBR_FMT);
+ return 0;
+ }
default:
if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
(pmc = get_fixed_pmc(pmu, msr))) {
@@ -370,6 +384,8 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
return 0;
}
break;
+ case MSR_IA32_PERF_CAPABILITIES:
+ return 1; /* RO MSR */
default:
if ((pmc = get_gp_pmc(pmu, msr, MSR_IA32_PERFCTR0)) ||
(pmc = get_fixed_pmc(pmu, msr))) {
--
2.7.4
next prev parent reply other threads:[~2019-02-14 9:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-14 9:06 [PATCH v5 00/12] Guest LBR Enabling Wei Wang
2019-02-14 9:06 ` [PATCH v5 01/12] perf/x86: fix the variable type of the LBR MSRs Wei Wang
2019-02-14 9:06 ` [PATCH v5 02/12] perf/x86: add a function to get the lbr stack Wei Wang
2019-02-14 9:06 ` [PATCH v5 03/12] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2019-02-14 16:21 ` Andi Kleen
2019-02-14 9:06 ` [PATCH v5 04/12] KVM/x86: intel_pmu_lbr_enable Wei Wang
2019-02-14 9:06 ` [PATCH v5 05/12] KVM/x86/vPMU: tweak kvm_pmu_get_msr Wei Wang
2019-02-14 9:06 ` Wei Wang [this message]
2019-02-14 9:06 ` [PATCH v5 07/12] perf/x86: no counter allocation support Wei Wang
2019-02-14 16:26 ` Andi Kleen
2019-02-15 8:49 ` Wang, Wei W
2019-02-14 9:06 ` [PATCH v5 08/12] KVM/x86/vPMU: Add APIs to support host save/restore the guest lbr stack Wei Wang
2019-02-14 9:06 ` [PATCH v5 09/12] perf/x86: save/restore LBR_SELECT on vCPU switching Wei Wang
2019-02-14 9:06 ` [PATCH v5 10/12] KVM/x86/lbr: lazy save the guest lbr stack Wei Wang
2019-02-15 1:49 ` Like Xu
2019-02-15 9:00 ` Wang, Wei W
2019-02-14 9:06 ` [PATCH v5 11/12] KVM/x86: remove the common handling of the debugctl msr Wei Wang
2019-02-14 9:06 ` [PATCH v5 12/12] KVM/VMX/vPMU: support to report GLOBAL_STATUS_LBRS_FROZEN Wei Wang
2019-02-14 16:31 ` Andi Kleen
2019-02-15 8:56 ` Wang, Wei W
2019-02-15 13:10 ` Andi Kleen
2019-02-18 1:59 ` Wei Wang
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