From: tip-bot for Yazen Ghannam <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, tglx@linutronix.de,
linux-edac@vger.kernel.org, mingo@kernel.org, bp@suse.de,
yazen.ghannam@amd.com, mchehab@kernel.org
Subject: [tip:ras/core] EDAC/mce_amd: Decode MCA_STATUS in bit definition order
Date: Fri, 15 Feb 2019 05:41:03 -0800 [thread overview]
Message-ID: <tip-a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67@git.kernel.org> (raw)
In-Reply-To: <20190212212417.107049-2-Yazen.Ghannam@amd.com>
Commit-ID: a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67
Gitweb: https://git.kernel.org/tip/a0bcd3c0b8a52ba0eb74371fa6be15ad0390ba67
Author: Yazen Ghannam <yazen.ghannam@amd.com>
AuthorDate: Tue, 12 Feb 2019 21:24:29 +0000
Committer: Borislav Petkov <bp@suse.de>
CommitDate: Fri, 15 Feb 2019 14:36:31 +0100
EDAC/mce_amd: Decode MCA_STATUS in bit definition order
Sort the MCA_STATUS bits in decode output to follow how they are defined
in the register.
The order is as follows:
Bit | Decode
------------
62 | Over
61 | UC
59 | MiscV
58 | AddrV
57 | PCC
55 | TCC
53 | SyndV
46 | CECC
45 | UECC
44 | Deferred
43 | Poison
40 | Scrub
[ bp: Massage a bit. ]
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86@kernel.org
Link: https://lkml.kernel.org/r/20190212212417.107049-2-Yazen.Ghannam@amd.com
---
drivers/edac/mce_amd.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/mce_amd.c b/drivers/edac/mce_amd.c
index b349c22bb386..0a1814dad6cf 100644
--- a/drivers/edac/mce_amd.c
+++ b/drivers/edac/mce_amd.c
@@ -1051,26 +1051,18 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
((m->status & MCI_STATUS_UC) ? "UE" :
(m->status & MCI_STATUS_DEFERRED) ? "-" : "CE"),
((m->status & MCI_STATUS_MISCV) ? "MiscV" : "-"),
- ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"),
- ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"));
-
- if (fam >= 0x15) {
- pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
-
- /* F15h, bank4, bit 43 is part of McaStatSubCache. */
- if (fam != 0x15 || m->bank != 4)
- pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
- }
+ ((m->status & MCI_STATUS_ADDRV) ? "AddrV" : "-"),
+ ((m->status & MCI_STATUS_PCC) ? "PCC" : "-"));
if (boot_cpu_has(X86_FEATURE_SMCA)) {
u32 low, high;
u32 addr = MSR_AMD64_SMCA_MCx_CONFIG(m->bank);
- pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
-
if (!rdmsr_safe(addr, &low, &high) &&
(low & MCI_CONFIG_MCAX))
pr_cont("|%s", ((m->status & MCI_STATUS_TCC) ? "TCC" : "-"));
+
+ pr_cont("|%s", ((m->status & MCI_STATUS_SYNDV) ? "SyndV" : "-"));
}
/* do the two bits[14:13] together */
@@ -1078,6 +1070,14 @@ amd_decode_mce(struct notifier_block *nb, unsigned long val, void *data)
if (ecc)
pr_cont("|%sECC", ((ecc == 2) ? "C" : "U"));
+ if (fam >= 0x15) {
+ pr_cont("|%s", (m->status & MCI_STATUS_DEFERRED ? "Deferred" : "-"));
+
+ /* F15h, bank4, bit 43 is part of McaStatSubCache. */
+ if (fam != 0x15 || m->bank != 4)
+ pr_cont("|%s", (m->status & MCI_STATUS_POISON ? "Poison" : "-"));
+ }
+
if (fam >= 0x17)
pr_cont("|%s", (m->status & MCI_STATUS_SCRUB ? "Scrub" : "-"));
next prev parent reply other threads:[~2019-02-15 13:41 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-12 21:24 [PATCH 1/2] EDAC/mce_amd: Decode MCA_STATUS[Scrub] bit Ghannam, Yazen
2019-02-12 21:24 ` [PATCH 2/2] EDAC/mce_amd: Decode MCA_STATUS in bit definition order Ghannam, Yazen
2019-02-15 13:41 ` tip-bot for Yazen Ghannam [this message]
2019-02-15 13:40 ` [tip:ras/core] EDAC/mce_amd: Decode MCA_STATUS[Scrub] bit tip-bot for Yazen Ghannam
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