From: Daniel Lezcano <daniel.lezcano@linaro.org>
To: tglx@linutronix.de
Cc: linux-kernel@vger.kernel.org, Joseph Lo <josephl@nvidia.com>,
devicetree@vger.kernel.org, Jon Hunter <jonathanh@nvidia.com>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Thierry Reding <thierry.reding@gmail.com>,
linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE
SUPPORT)
Subject: [PATCH 16/18] dt-bindings: timer: add Tegra210 timer
Date: Sat, 23 Feb 2019 14:07:04 +0100 [thread overview]
Message-ID: <20190223130707.16704-16-daniel.lezcano@linaro.org> (raw)
In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org>
From: Joseph Lo <josephl@nvidia.com>
The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
(TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
or watchdog interrupts.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-kernel@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
---
.../bindings/timer/nvidia,tegra210-timer.txt | 36 +++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
diff --git a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
new file mode 100644
index 000000000000..032cda96fe0d
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
@@ -0,0 +1,36 @@
+NVIDIA Tegra210 timer
+
+The Tegra210 timer provides fourteen 29-bit timer counters and one 32-bit
+timestamp counter. The TMRs run at either a fixed 1 MHz clock rate derived
+from the oscillator clock (TMR0-TMR9) or directly at the oscillator clock
+(TMR10-TMR13). Each TMR can be programmed to generate one-shot, periodic,
+or watchdog interrupts.
+
+Required properties:
+- compatible : "nvidia,tegra210-timer".
+- reg : Specifies base physical address and size of the registers.
+- interrupts : A list of 14 interrupts; one per each timer channels 0 through
+ 13.
+- clocks : Must contain one entry, for the module clock.
+ See ../clocks/clock-bindings.txt for details.
+
+timer@60005000 {
+ compatible = "nvidia,tegra210-timer";
+ reg = <0x0 0x60005000 0x0 0x400>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&tegra_car TEGRA210_CLK_TIMER>;
+ clock-names = "timer";
+};
--
2.17.1
next prev parent reply other threads:[~2019-02-23 13:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-23 13:05 [GIT PULL] clockevents for 5.1 Daniel Lezcano
2019-02-23 13:06 ` [PATCH 01/18] clocksource/drivers/sun5i: Fail gracefully when clock rate is unavailable Daniel Lezcano
2019-02-23 13:06 ` [PATCH 02/18] clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability Daniel Lezcano
[not found] ` <20190226212356.C6B68218A2@mail.kernel.org>
2019-02-27 2:55 ` Samuel Holland
2019-02-23 13:06 ` [PATCH 03/18] clocksource/drivers/exynos_mct: Move one-shot check from tick clear to ISR Daniel Lezcano
2019-02-23 13:06 ` [PATCH 04/18] clocksource/drivers/exynos_mct: Clear timer interrupt when shutdown Daniel Lezcano
2019-02-23 13:06 ` [PATCH 05/18] dt-bindings: timer: renesas, cmt: Document r8a774c0 CMT support Daniel Lezcano
2019-02-23 13:06 ` [PATCH 06/18] dt-bindings: timer: renesas: tmu: Document r8a774c0 bindings Daniel Lezcano
2019-02-23 13:06 ` [PATCH 07/18] clocksource/drivers/riscv: Add required checks during clock source init Daniel Lezcano
2019-02-23 13:06 ` [PATCH 08/18] clocksource/drivers/exynos_mct: Remove dead code Daniel Lezcano
2019-02-23 13:06 ` [PATCH 09/18] clocksource/drivers/exynos_mct: Fix error path in timer resources initialization Daniel Lezcano
2019-02-23 13:06 ` [PATCH 10/18] dt-bindings: timer: mediatek: update bindings for MT7629 SoC Daniel Lezcano
2019-02-23 13:06 ` [PATCH 11/18] clocksource/drivers/exynos_mct: Remove unused header includes Daniel Lezcano
2019-02-23 13:07 ` [PATCH 12/18] dt-bindings: timer: gpt: update binding doc Daniel Lezcano
2019-02-23 13:07 ` [PATCH 13/18] clocksource/drivers/tango-xtal: Rename the file for consistency Daniel Lezcano
2019-02-23 13:07 ` [PATCH 14/18] clocksource/drivers/timer-pxa: " Daniel Lezcano
2019-02-23 13:07 ` [PATCH 15/18] clocksource/drivers/timer-cs5535: " Daniel Lezcano
2019-02-23 13:07 ` Daniel Lezcano [this message]
2019-02-23 13:07 ` [PATCH 17/18] clocksource/drivers/tegra: Add Tegra210 timer support Daniel Lezcano
2019-02-23 13:07 ` [PATCH 18/18] soc/tegra: default select TEGRA_TIMER for Tegra210 Daniel Lezcano
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