From: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To: "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
Cc: "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@alien8.de" <bp@alien8.de>
Subject: [PATCH v2 4/6] EDAC/amd64: Recognize x16 Symbol Size
Date: Tue, 26 Feb 2019 17:25:47 +0000 [thread overview]
Message-ID: <20190226172532.12924-4-Yazen.Ghannam@amd.com> (raw)
In-Reply-To: <20190226172532.12924-1-Yazen.Ghannam@amd.com>
From: Yazen Ghannam <yazen.ghannam@amd.com>
Future AMD systems may support x16 symbol sizes.
Recognize if a system is using x16 symbol size. Also, simplify the print
statement.
Note that a x16 syndrome vector table is not necessary like with x4 or
x8. This is because systems that support x16 symbol sizes will be SMCA
systems. In which case, the syndrome can be directly extracted from the
MCA_SYND[Syndrome] field.
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190219202536.15462-3-Yazen.Ghannam@amd.com
v1->v2:
* Apply Boris' fixup.
drivers/edac/amd64_edac.c | 21 ++++++++++-----------
drivers/edac/amd64_edac.h | 2 +-
2 files changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c82aafb7246a..810345572808 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -897,8 +897,7 @@ static void dump_misc_regs(struct amd64_pvt *pvt)
edac_dbg(1, " DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
- amd64_info("using %s syndromes.\n",
- ((pvt->ecc_sym_sz == 8) ? "x8" : "x4"));
+ amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
}
/*
@@ -2609,17 +2608,17 @@ static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
for_each_umc(i) {
/* Check enabled channels only: */
- if ((pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) &&
- (pvt->umc[i].ecc_ctrl & BIT(7))) {
- pvt->ecc_sym_sz = 8;
- break;
+ if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
+ if (pvt->umc[i].ecc_ctrl & BIT(9)) {
+ pvt->ecc_sym_sz = 16;
+ return;
+ } else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
+ pvt->ecc_sym_sz = 8;
+ return;
+ }
}
}
-
- return;
- }
-
- if (pvt->fam >= 0x10) {
+ } else if (pvt->fam >= 0x10) {
u32 tmp;
amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 40e63cea2d81..44d81eccfe0a 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -370,7 +370,7 @@ struct amd64_pvt {
u32 dct_sel_hi; /* DRAM Controller Select High */
u32 online_spare; /* On-Line spare Reg */
- /* x4 or x8 syndromes in use */
+ /* x4, x8, or x16 syndromes in use */
u8 ecc_sym_sz;
/* place to store error injection parameters prior to issue */
--
2.17.1
next prev parent reply other threads:[~2019-02-26 17:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-26 17:25 [PATCH v2 1/6] EDAC/amd64: Add Family 17h Model 30h PCI IDs Ghannam, Yazen
2019-02-26 17:25 ` [PATCH v2 2/6] EDAC/amd64: Support more than two Unified Memory Controllers Ghannam, Yazen
2019-02-26 17:25 ` [PATCH v2 3/6] EDAC/amd64: Use a macro for iterating over " Ghannam, Yazen
2019-02-26 21:53 ` Borislav Petkov
2019-02-27 14:50 ` Ghannam, Yazen
2019-02-26 17:25 ` Ghannam, Yazen [this message]
2019-02-26 17:25 ` [PATCH v2 5/6] EDAC/amd64: Support more than two Controllers for Chip Select handling Ghannam, Yazen
2019-02-26 17:25 ` [PATCH v2 6/6] EDAC/amd64: Adjust printed Chip Select sizes when interleaved Ghannam, Yazen
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