From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC
Date: Tue, 5 Mar 2019 11:19:06 +0100 [thread overview]
Message-ID: <1551781151-5562-4-git-send-email-l.luba@partner.samsung.com> (raw)
In-Reply-To: <1551781151-5562-1-git-send-email-l.luba@partner.samsung.com>
Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 6da5875..6f5db70 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1331,6 +1331,17 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini
PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
};
+static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = {
+ PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1),
+ PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1),
+ PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2),
+ PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2),
+ PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3),
+ PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3),
+};
+
static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
@@ -1473,7 +1484,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
- exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
+ exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table;
}
samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
--
2.7.4
next prev parent reply other threads:[~2019-03-05 10:20 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190305101924eucas1p24a058fcc034cc95bc33888087412ab48@eucas1p2.samsung.com>
2019-03-05 10:19 ` [PATCH v5 0/8] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190305101924eucas1p1147e3895a89a72c9db7d128d90dd3daa@eucas1p1.samsung.com>
2019-03-05 10:19 ` [PATCH v5 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-03-11 22:06 ` Rob Herring
2019-03-12 9:18 ` Lukasz Luba
[not found] ` <CGME20190305101925eucas1p22d36ab220829bc6df98c92bb6c5e0395@eucas1p2.samsung.com>
2019-03-05 10:19 ` [PATCH v5 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-03-06 8:11 ` Chanwoo Choi
[not found] ` <CGME20190305101926eucas1p158d6241bd6851b3d98ed9aae6cba502c@eucas1p1.samsung.com>
2019-03-05 10:19 ` Lukasz Luba [this message]
2019-03-06 1:31 ` [PATCH v5 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Chanwoo Choi
2019-03-06 7:05 ` Lukasz Luba
[not found] ` <CGME20190305101926eucas1p2eee36b9cb50cbcf511fab7bae59e24bb@eucas1p2.samsung.com>
2019-03-05 10:19 ` [PATCH v5 4/8] dt-bindings: devfreq: add Exynos5422 DMC device description Lukasz Luba
2019-03-05 11:35 ` Krzysztof Kozlowski
2019-03-06 7:35 ` Lukasz Luba
2019-03-06 4:18 ` Chanwoo Choi
2019-03-06 7:14 ` Lukasz Luba
2019-03-06 7:50 ` Chanwoo Choi
2019-03-07 13:40 ` Sylwester Nawrocki
[not found] ` <CGME20190305101927eucas1p151816366df5b2071ca73dd7194b70799@eucas1p1.samsung.com>
2019-03-05 10:19 ` [PATCH v5 5/8] drivers: devfreq: add DMC driver for Exynos5422 Lukasz Luba
2019-03-06 7:57 ` Chanwoo Choi
[not found] ` <CGME20190305101927eucas1p250bbcbccb43590edd2b9ccf06cce2023@eucas1p2.samsung.com>
2019-03-05 10:19 ` [PATCH v5 6/8] DT: arm: exynos: add DMC device for exynos5422 Lukasz Luba
2019-03-05 11:36 ` Krzysztof Kozlowski
2019-03-06 7:24 ` Lukasz Luba
[not found] ` <CGME20190305101928eucas1p2032dea7512be3d57618842d65e67bc8f@eucas1p2.samsung.com>
2019-03-05 10:19 ` [PATCH v5 7/8] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190305101929eucas1p1dd30eee4c28dce142573e21d08c9abbd@eucas1p1.samsung.com>
2019-03-05 10:19 ` [PATCH v5 8/8] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1551781151-5562-4-git-send-email-l.luba@partner.samsung.com \
--to=l.luba@partner.samsung.com \
--cc=b.zolnierkie@samsung.com \
--cc=cw00.choi@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=kgene@kernel.org \
--cc=krzk@kernel.org \
--cc=kyungmin.park@samsung.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=m.szyprowski@samsung.com \
--cc=myungjoo.ham@samsung.com \
--cc=s.nawrocki@samsung.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).