From: Icenowy Zheng <icenowy@aosc.io>
To: Maxime Ripard <maxime.ripard@bootlin.com>, Chen-Yu Tsai <wens@csie.org>
Cc: linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
Icenowy Zheng <icenowy@aosc.io>
Subject: [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset
Date: Thu, 14 Mar 2019 19:21:08 +0800 [thread overview]
Message-ID: <20190314112108.6150-1-icenowy@aosc.io> (raw)
The bit offset of the USB PHY clock gate on F1C100s should be 1, not 8.
Fix this problem.
Fixes: 0380126eb9af ("clk: sunxi-ng: add support for suniv F1C100s SoC")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
index a09dfbe36402..dc9f0a365664 100644
--- a/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
+++ b/drivers/clk/sunxi-ng/ccu-suniv-f1c100s.c
@@ -240,7 +240,7 @@ static SUNXI_CCU_MUX_WITH_GATE(spdif_clk, "spdif", i2s_spdif_parents,
/* The BSP header file has a CIR_CFG, but no mod clock uses this definition */
static SUNXI_CCU_GATE(usb_phy0_clk, "usb-phy0", "osc24M",
- 0x0cc, BIT(8), 0);
+ 0x0cc, BIT(1), 0);
static SUNXI_CCU_GATE(dram_ve_clk, "dram-ve", "pll-ddr",
0x100, BIT(0), 0);
--
2.18.1
next reply other threads:[~2019-03-14 11:21 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-14 11:21 Icenowy Zheng [this message]
2019-03-14 15:46 ` [PATCH] clk: sunxi-ng: f1c100s: fix USB PHY gate bit offset Maxime Ripard
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