From: kan.liang@linux.intel.com
To: peterz@infradead.org, acme@kernel.org, mingo@redhat.com,
linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com,
Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V4 18/23] perf/x86/intel: Disable sampling read slots and topdown
Date: Tue, 26 Mar 2019 09:08:56 -0700 [thread overview]
Message-ID: <20190326160901.4887-19-kan.liang@linux.intel.com> (raw)
In-Reply-To: <20190326160901.4887-1-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
To get correct PERF_METRICS value, the fixed counter 3 must start from
0. It would bring problems when sampling read slots and topdown events.
For example,
perf record -e '{slots, topdown-retiring}:S'
The slots would not overflow if it starts from 0.
Add specific validate_group() support to reject the case and error out
for Icelake.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
No changes since V3.
arch/x86/events/core.c | 2 ++
arch/x86/events/intel/core.c | 20 ++++++++++++++++++++
arch/x86/events/perf_event.h | 2 ++
3 files changed, 24 insertions(+)
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 7d4d56f76436..b9bee53e53d8 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2122,6 +2122,8 @@ static int validate_group(struct perf_event *event)
ret = x86_pmu.schedule_events(fake_cpuc, n, NULL);
+ if (x86_pmu.validate_group)
+ ret = x86_pmu.validate_group(fake_cpuc, n);
out:
free_fake_cpuc(fake_cpuc);
return ret;
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index b08e361fc718..ef6045544628 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -4331,6 +4331,25 @@ static int icl_set_period(struct perf_event *event)
return 1;
}
+static int icl_validate_group(struct cpu_hw_events *cpuc, int n)
+{
+ bool has_sampling_slots = false, has_metrics = false;
+ struct perf_event *e;
+ int i;
+
+ for (i = 0; i < n; i++) {
+ e = cpuc->event_list[i];
+ if (is_slots_event(e) && is_sampling_event(e))
+ has_sampling_slots = true;
+
+ if (is_perf_metrics_event(e))
+ has_metrics = true;
+ }
+ if (unlikely(has_sampling_slots && has_metrics))
+ return -EINVAL;
+ return 0;
+}
+
EVENT_ATTR_STR(mem-loads, mem_ld_hsw, "event=0xcd,umask=0x1,ldlat=3");
EVENT_ATTR_STR(mem-stores, mem_st_hsw, "event=0xd0,umask=0x82")
@@ -5037,6 +5056,7 @@ __init int intel_pmu_init(void)
x86_pmu.has_metric = x86_pmu.intel_cap.perf_metrics;
x86_pmu.metric_update_event = icl_metric_update_event;
x86_pmu.set_period = icl_set_period;
+ x86_pmu.validate_group = icl_validate_group;
pr_cont("Icelake events, ");
name = "icelake";
break;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 6500463bda85..077d44a96d31 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -631,6 +631,8 @@ struct x86_pmu {
u64 (*limit_period)(struct perf_event *event, u64 l);
int (*set_period)(struct perf_event *event);
+ int (*validate_group)(struct cpu_hw_events *cpuc, int n);
+
/* PMI handler bits */
unsigned int late_ack :1,
counter_freezing :1;
--
2.17.1
next prev parent reply other threads:[~2019-03-26 16:12 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-26 16:08 [PATCH V4 00/23] perf: Add Icelake support kan.liang
2019-03-26 16:08 ` [PATCH V4 01/23] perf/x86: Support outputting XMM registers kan.liang
2019-04-01 19:18 ` Stephane Eranian
2019-04-01 19:54 ` Liang, Kan
2019-04-01 21:11 ` Stephane Eranian
2019-04-01 22:33 ` Liang, Kan
2019-03-26 16:08 ` [PATCH V4 02/23] perf/x86/intel: Extract memory code PEBS parser for reuse kan.liang
2019-03-26 16:08 ` [PATCH V4 03/23] perf/x86/intel/ds: Extract code of event update in short period kan.liang
2019-03-26 16:08 ` [PATCH V4 04/23] perf/x86/intel: Support adaptive PEBSv4 kan.liang
2019-03-26 22:24 ` Andi Kleen
2019-03-27 14:25 ` Liang, Kan
2019-03-27 14:42 ` Andi Kleen
2019-03-26 16:08 ` [PATCH V4 05/23] perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them kan.liang
2019-03-26 16:08 ` [PATCH V4 06/23] perf/x86: Support constraint ranges kan.liang
2019-03-26 16:08 ` [PATCH V4 07/23] perf/x86/intel: Add Icelake support kan.liang
2019-03-26 16:08 ` [PATCH V4 08/23] perf/x86/intel/cstate: " kan.liang
2019-03-26 16:08 ` [PATCH V4 09/23] perf/x86/intel/rapl: " kan.liang
2019-03-26 16:08 ` [PATCH V4 10/23] perf/x86/msr: " kan.liang
2019-03-26 16:08 ` [PATCH V4 11/23] perf/x86/intel/uncore: Add Intel Icelake uncore support kan.liang
2019-03-26 16:08 ` [PATCH V4 12/23] perf/core: Support a REMOVE transaction kan.liang
2019-03-26 16:08 ` [PATCH V4 13/23] perf/x86/intel: Basic support for metrics counters kan.liang
2019-03-26 16:08 ` [PATCH V4 14/23] perf/x86/intel: Support overflows on SLOTS kan.liang
2019-03-26 16:08 ` [PATCH V4 15/23] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-03-26 16:08 ` [PATCH V4 16/23] perf/x86/intel: Set correct weight for topdown subevent counters kan.liang
2019-03-26 16:08 ` [PATCH V4 17/23] perf/x86/intel: Export new top down events for Icelake kan.liang
2019-03-26 16:08 ` kan.liang [this message]
2019-03-26 16:08 ` [PATCH V4 19/23] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
2019-03-26 16:08 ` [PATCH V4 20/23] perf, tools: Add support for recording and printing XMM registers kan.liang
2019-03-26 16:08 ` [PATCH V4 21/23] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-03-26 16:09 ` [PATCH V4 22/23] perf, tools: Add documentation for topdown metrics kan.liang
2019-03-26 16:09 ` [PATCH V4 23/23] perf vendor events intel: Add JSON files for Icelake kan.liang
2019-04-01 13:01 ` [PATCH V4 00/23] perf: Add Icelake support Liang, Kan
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