From: Sibi Sankar <sibis@codeaurora.org>
To: robh+dt@kernel.org, andy.gross@linaro.org,
myungjoo.ham@samsung.com, kyungmin.park@samsung.com,
rjw@rjwysocki.net, viresh.kumar@linaro.org, nm@ti.com,
sboyd@kernel.org, georgi.djakov@linaro.org
Cc: bjorn.andersson@linaro.org, david.brown@linaro.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org,
linux-arm-msm-owner@vger.kernel.org, devicetree@vger.kernel.org,
rnayak@codeaurora.org, cw00.choi@samsung.com,
linux-pm@vger.kernel.org, evgreen@chromium.org,
daidavid1@codeaurora.org, dianders@chromium.org,
Sibi Sankar <sibis@codeaurora.org>
Subject: [PATCH RFC 9/9] arm64: dts: qcom: sdm845: Add nodes for icbw driver and opp tables
Date: Thu, 28 Mar 2019 20:58:22 +0530 [thread overview]
Message-ID: <20190328152822.532-10-sibis@codeaurora.org> (raw)
In-Reply-To: <20190328152822.532-1-sibis@codeaurora.org>
Add nodes to enable DDR devfreq driver on SDM845 SoC.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 80 ++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 072563f6b6cb..21a0068855e8 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/clock/qcom,lpass-sdm845.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qusb2.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@@ -488,6 +489,85 @@
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpubw: cpu-icbw {
+ compatible = "devfreq-icbw";
+ interconnects = <&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_EBI1>;
+ operating-points-v2 = <&bw_opp_table>;
+ };
+
+ bw_opp_table: bw-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200 {
+ opp-hz = /bits/ 64 < 200000000 >; /* 200 MHz */
+ required-opps = <&cpu0_opp1>;
+ /* 0 MB/s average and 762 MB/s peak bandwidth */
+ opp-bw-MBs = <0 762>;
+ };
+
+ opp-300 {
+ opp-hz = /bits/ 64 < 300000000 >; /* 300 MHz */
+ /* 0 MB/s average and 1144 MB/s peak bandwidth */
+ opp-bw-MBs = <0 1144>;
+ };
+
+ opp-451 {
+ opp-hz = /bits/ 64 < 451000000 >; /* 451 MHz */
+ /* 0 MB/s average and 1720 MB/s peak bandwidth */
+ opp-bw-MBs = <0 1720>;
+ required-opps = <&cpu0_opp6>;
+ };
+
+ opp-547 {
+ opp-hz = /bits/ 64 < 547000000 >; /* 547 MHz */
+ /* 0 MB/s average and 2086 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2086>;
+ required-opps = <&cpu0_opp11>;
+ };
+
+ opp-681 {
+ opp-hz = /bits/ 64 < 681000000 >; /* 681 MHz */
+ /* 0 MB/s average and 2597 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2597>;
+ required-opps = <&cpu0_opp15>;
+ };
+
+ opp-768 {
+ opp-hz = /bits/ 64 < 768000000 >; /* 768 MHz */
+ /* 0 MB/s average and 2929 MB/s peak bandwidth */
+ opp-bw-MBs = <0 2929>;
+ required-opps = <&cpu4_opp4>;
+ };
+
+ opp-1017 {
+ opp-hz = /bits/ 64 < 1017000000 >; /* 1017 MHz */
+ /* 0 MB/s average and 3879 MB/s peak bandwidth */
+ opp-bw-MBs = <0 3879>;
+ required-opps = <&cpu0_opp16>, <&cpu4_opp5>;
+ };
+
+ opp-1296 {
+ opp-hz = /bits/ 64 < 1296000000 >; /* 1296 MHz */
+ /* 0 MB/s average and 4943 MB/s peak bandwidth */
+ opp-bw-MBs = <0 4943>;
+ required-opps = <&cpu4_opp10>;
+ };
+
+ opp-1555 {
+ opp-hz = /bits/ 64 < 1555000000 >; /* 1555 MHz */
+ /* 0 MB/s average and 5931 MB/s peak bandwidth */
+ opp-bw-MBs = <0 5931>;
+ required-opps = <&cpu4_opp12>;
+ };
+
+ opp-1804 {
+ opp-hz = /bits/ 64 < 1804000000 >; /* 1804 MHz */
+ /* 0 MB/s average and 6881 MB/s peak bandwidth */
+ opp-bw-MBs = <0 6881>;
+ required-opps = <&cpu4_opp15>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2019-03-28 15:29 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-28 15:28 [PATCH RFC 0/9] Add CPU based scaling support to Passive governor Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 1/9] OPP: Add and export helpers to get avg/peak bw Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 2/9] OPP: Export a number of helpers to prevent code duplication Sibi Sankar
2019-07-08 3:28 ` Hsin-Yi Wang
2019-07-10 8:01 ` Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 3/9] PM / devfreq: Add cpu based scaling support to passive_governor Sibi Sankar
2019-04-12 7:39 ` Chanwoo Choi
2019-05-27 8:23 ` Sibi Sankar
2019-05-28 1:27 ` Chanwoo Choi
2019-03-28 15:28 ` [PATCH RFC 4/9] dt-bindings: devfreq: Add bindings for devfreq dev-icbw driver Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 5/9] PM / devfreq: Add devfreq driver for interconnect bandwidth voting Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 6/9] OPP: Add and export helper to update voltage Sibi Sankar
2019-04-10 10:24 ` Viresh Kumar
2019-04-10 11:08 ` Sibi Sankar
2019-03-28 15:28 ` [PATCH RFC 7/9] cpufreq: qcom: Add support to update cpu node's OPP tables Sibi Sankar
2019-04-10 10:33 ` Viresh Kumar
2019-04-10 11:16 ` Sibi Sankar
2019-04-10 11:25 ` Viresh Kumar
2019-03-28 15:28 ` [PATCH RFC 8/9] arm64: dts: qcom: sdm845: Add cpu " Sibi Sankar
2019-03-28 15:28 ` Sibi Sankar [this message]
2019-04-11 7:02 ` [PATCH RFC 0/9] Add CPU based scaling support to Passive governor Sibi Sankar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20190328152822.532-10-sibis@codeaurora.org \
--to=sibis@codeaurora.org \
--cc=andy.gross@linaro.org \
--cc=bjorn.andersson@linaro.org \
--cc=cw00.choi@samsung.com \
--cc=daidavid1@codeaurora.org \
--cc=david.brown@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=dianders@chromium.org \
--cc=evgreen@chromium.org \
--cc=georgi.djakov@linaro.org \
--cc=kyungmin.park@samsung.com \
--cc=linux-arm-msm-owner@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=myungjoo.ham@samsung.com \
--cc=nm@ti.com \
--cc=rjw@rjwysocki.net \
--cc=rnayak@codeaurora.org \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=viresh.kumar@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).