From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: linux-arm-kernel@lists.infradead.org
Cc: alexander.shishkin@linux.intel.com, peterz@infradead.org,
suzuki.poulose@arm.com, mike.leach@arm.com, leo.yan@linaro.org,
coresight@lists.linaro.org, linux-kernel@vger.kernel.org
Subject: [PATCH v3 07/20] coresight: Properly address errors in sink::disable() functions
Date: Wed, 3 Apr 2019 21:35:28 -0600 [thread overview]
Message-ID: <20190404033541.14072-8-mathieu.poirier@linaro.org> (raw)
In-Reply-To: <20190404033541.14072-1-mathieu.poirier@linaro.org>
When disabling a sink the reference counter ensures the operation goes
through if nobody else is using it. As such if drvdata::mode is already
set do CS_MODE_DISABLED, it is an error and should be reported as such.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/hwtracing/coresight/coresight-etb10.c | 9 ++++-----
drivers/hwtracing/coresight/coresight-tmc-etf.c | 9 ++++-----
drivers/hwtracing/coresight/coresight-tmc-etr.c | 9 ++++-----
3 files changed, 12 insertions(+), 15 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etb10.c b/drivers/hwtracing/coresight/coresight-etb10.c
index 5af50a852e87..52b7d95ab498 100644
--- a/drivers/hwtracing/coresight/coresight-etb10.c
+++ b/drivers/hwtracing/coresight/coresight-etb10.c
@@ -341,11 +341,10 @@ static int etb_disable(struct coresight_device *csdev)
return -EBUSY;
}
- /* Disable the ETB only if it needs to */
- if (drvdata->mode != CS_MODE_DISABLED) {
- etb_disable_hw(drvdata);
- drvdata->mode = CS_MODE_DISABLED;
- }
+ /* Complain if we (somehow) got out of sync */
+ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED);
+ etb_disable_hw(drvdata);
+ drvdata->mode = CS_MODE_DISABLED;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
dev_dbg(drvdata->dev, "ETB disabled\n");
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etf.c b/drivers/hwtracing/coresight/coresight-tmc-etf.c
index d50a608a60f1..30f868676540 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etf.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etf.c
@@ -297,11 +297,10 @@ static int tmc_disable_etf_sink(struct coresight_device *csdev)
return -EBUSY;
}
- /* Disable the TMC only if it needs to */
- if (drvdata->mode != CS_MODE_DISABLED) {
- tmc_etb_disable_hw(drvdata);
- drvdata->mode = CS_MODE_DISABLED;
- }
+ /* Complain if we (somehow) got out of sync */
+ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED);
+ tmc_etb_disable_hw(drvdata);
+ drvdata->mode = CS_MODE_DISABLED;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index f90bca971367..86e748d09dc3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -1416,11 +1416,10 @@ static int tmc_disable_etr_sink(struct coresight_device *csdev)
return -EBUSY;
}
- /* Disable the TMC only if it needs to */
- if (drvdata->mode != CS_MODE_DISABLED) {
- tmc_etr_disable_hw(drvdata);
- drvdata->mode = CS_MODE_DISABLED;
- }
+ /* Complain if we (somehow) got out of sync */
+ WARN_ON_ONCE(drvdata->mode == CS_MODE_DISABLED);
+ tmc_etr_disable_hw(drvdata);
+ drvdata->mode = CS_MODE_DISABLED;
spin_unlock_irqrestore(&drvdata->spinlock, flags);
--
2.17.1
next prev parent reply other threads:[~2019-04-04 3:36 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 3:35 [PATCH v3 00/20] coresight: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 01/20] coresight: pmu: Adding ITRACE property to cs_etm PMU Mathieu Poirier
2019-04-04 8:48 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 02/20] coresight: etm4x: Add kernel configuration for CONTEXTID Mathieu Poirier
2019-04-04 8:53 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 03/20] coresight: etm4x: Skip selector pair 0 Mathieu Poirier
2019-04-04 8:50 ` Suzuki K Poulose
2019-04-04 3:35 ` [PATCH v3 04/20] coresight: etm4x: Configure tracers to emit timestamps Mathieu Poirier
2019-04-04 4:47 ` Mike Leach
2019-04-04 3:35 ` [PATCH v3 05/20] coresight: Adding return code to sink::disable() operation Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 06/20] coresight: Move reference counting inside sink drivers Mathieu Poirier
2019-04-04 3:35 ` Mathieu Poirier [this message]
2019-04-04 3:35 ` [PATCH v3 08/20] coresight: Properly address concurrency in sink::update() functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 09/20] coresight: perf: Clean up function etm_setup_aux() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 10/20] coresight: perf: Refactor function free_event_data() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 11/20] coresight: Communicate perf event to sink buffer allocation functions Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 12/20] coresight: tmc-etr: Refactor function tmc_etr_setup_perf_buf() Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 13/20] coresight: tmc-etr: Create per-thread buffer allocation function Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 14/20] coresight: tmc-etr: Introduce the notion of process ID to ETR devices Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 15/20] coresight: tmc-etr: Introduce the notion of reference counting " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 16/20] coresight: tmc-etr: Introduce the notion of IDR " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 17/20] coresight: tmc-etr: Allocate and free ETR memory buffers for CPU-wide scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 18/20] coresight: tmc-etr: Add support for CPU-wide trace scenarios Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 19/20] coresight: tmc-etf: " Mathieu Poirier
2019-04-04 3:35 ` [PATCH v3 20/20] coresight: etb10: " Mathieu Poirier
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