From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-arm-kernel@lists.infradead.org
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@redhat.com>, Namhyung Kim <namhyung@kernel.org>,
Will Deacon <will.deacon@arm.com>,
Mark Rutland <mark.rutland@arm.com>,
Catalin Marinas <catalin.marinas@arm.com>,
linux-kernel@vger.kernel.org (open list:PERFORMANCE EVENTS
SUBSYSTEM)
Subject: [PATCH 1/2] arm64: perf: Group common ARMv8 v3 PMU events in a macro
Date: Thu, 4 Apr 2019 16:25:44 -0700 [thread overview]
Message-ID: <20190404232545.2627-2-f.fainelli@gmail.com> (raw)
In-Reply-To: <20190404232545.2627-1-f.fainelli@gmail.com>
In preparation for adding processor specific attributes, group the ARMv8
PMU v3 common events into a macro that can be re-used to fill up an
array of attributes.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm64/kernel/perf_event.c | 123 +++++++++++++++++----------------
1 file changed, 63 insertions(+), 60 deletions(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4addb38bc250..2d30922692b1 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -234,67 +234,70 @@ ARMV8_EVENT_ATTR(sample_feed, ARMV8_SPE_PERFCTR_SAMPLE_FEED);
ARMV8_EVENT_ATTR(sample_filtrate, ARMV8_SPE_PERFCTR_SAMPLE_FILTRATE);
ARMV8_EVENT_ATTR(sample_collision, ARMV8_SPE_PERFCTR_SAMPLE_COLLISION);
+#define ARMV8_PMUV3_EVENT_ATTRS \
+ &armv8_event_attr_sw_incr.attr.attr, \
+ &armv8_event_attr_l1i_cache_refill.attr.attr, \
+ &armv8_event_attr_l1i_tlb_refill.attr.attr, \
+ &armv8_event_attr_l1d_cache_refill.attr.attr, \
+ &armv8_event_attr_l1d_cache.attr.attr, \
+ &armv8_event_attr_l1d_tlb_refill.attr.attr, \
+ &armv8_event_attr_ld_retired.attr.attr, \
+ &armv8_event_attr_st_retired.attr.attr, \
+ &armv8_event_attr_inst_retired.attr.attr, \
+ &armv8_event_attr_exc_taken.attr.attr, \
+ &armv8_event_attr_exc_return.attr.attr, \
+ &armv8_event_attr_cid_write_retired.attr.attr, \
+ &armv8_event_attr_pc_write_retired.attr.attr, \
+ &armv8_event_attr_br_immed_retired.attr.attr, \
+ &armv8_event_attr_br_return_retired.attr.attr, \
+ &armv8_event_attr_unaligned_ldst_retired.attr.attr, \
+ &armv8_event_attr_br_mis_pred.attr.attr, \
+ &armv8_event_attr_cpu_cycles.attr.attr, \
+ &armv8_event_attr_br_pred.attr.attr, \
+ &armv8_event_attr_mem_access.attr.attr, \
+ &armv8_event_attr_l1i_cache.attr.attr, \
+ &armv8_event_attr_l1d_cache_wb.attr.attr, \
+ &armv8_event_attr_l2d_cache.attr.attr, \
+ &armv8_event_attr_l2d_cache_refill.attr.attr, \
+ &armv8_event_attr_l2d_cache_wb.attr.attr, \
+ &armv8_event_attr_bus_access.attr.attr, \
+ &armv8_event_attr_memory_error.attr.attr, \
+ &armv8_event_attr_inst_spec.attr.attr, \
+ &armv8_event_attr_ttbr_write_retired.attr.attr, \
+ &armv8_event_attr_bus_cycles.attr.attr, \
+ &armv8_event_attr_l1d_cache_allocate.attr.attr, \
+ &armv8_event_attr_l2d_cache_allocate.attr.attr, \
+ &armv8_event_attr_br_retired.attr.attr, \
+ &armv8_event_attr_br_mis_pred_retired.attr.attr, \
+ &armv8_event_attr_stall_frontend.attr.attr, \
+ &armv8_event_attr_stall_backend.attr.attr, \
+ &armv8_event_attr_l1d_tlb.attr.attr, \
+ &armv8_event_attr_l1i_tlb.attr.attr, \
+ &armv8_event_attr_l2i_cache.attr.attr, \
+ &armv8_event_attr_l2i_cache_refill.attr.attr, \
+ &armv8_event_attr_l3d_cache_allocate.attr.attr, \
+ &armv8_event_attr_l3d_cache_refill.attr.attr, \
+ &armv8_event_attr_l3d_cache.attr.attr, \
+ &armv8_event_attr_l3d_cache_wb.attr.attr, \
+ &armv8_event_attr_l2d_tlb_refill.attr.attr, \
+ &armv8_event_attr_l2i_tlb_refill.attr.attr, \
+ &armv8_event_attr_l2d_tlb.attr.attr, \
+ &armv8_event_attr_l2i_tlb.attr.attr, \
+ &armv8_event_attr_remote_access.attr.attr, \
+ &armv8_event_attr_ll_cache.attr.attr, \
+ &armv8_event_attr_ll_cache_miss.attr.attr, \
+ &armv8_event_attr_dtlb_walk.attr.attr, \
+ &armv8_event_attr_itlb_walk.attr.attr, \
+ &armv8_event_attr_ll_cache_rd.attr.attr, \
+ &armv8_event_attr_ll_cache_miss_rd.attr.attr, \
+ &armv8_event_attr_remote_access_rd.attr.attr, \
+ &armv8_event_attr_sample_pop.attr.attr, \
+ &armv8_event_attr_sample_feed.attr.attr, \
+ &armv8_event_attr_sample_filtrate.attr.attr, \
+ &armv8_event_attr_sample_collision.attr.attr, \
+
static struct attribute *armv8_pmuv3_event_attrs[] = {
- &armv8_event_attr_sw_incr.attr.attr,
- &armv8_event_attr_l1i_cache_refill.attr.attr,
- &armv8_event_attr_l1i_tlb_refill.attr.attr,
- &armv8_event_attr_l1d_cache_refill.attr.attr,
- &armv8_event_attr_l1d_cache.attr.attr,
- &armv8_event_attr_l1d_tlb_refill.attr.attr,
- &armv8_event_attr_ld_retired.attr.attr,
- &armv8_event_attr_st_retired.attr.attr,
- &armv8_event_attr_inst_retired.attr.attr,
- &armv8_event_attr_exc_taken.attr.attr,
- &armv8_event_attr_exc_return.attr.attr,
- &armv8_event_attr_cid_write_retired.attr.attr,
- &armv8_event_attr_pc_write_retired.attr.attr,
- &armv8_event_attr_br_immed_retired.attr.attr,
- &armv8_event_attr_br_return_retired.attr.attr,
- &armv8_event_attr_unaligned_ldst_retired.attr.attr,
- &armv8_event_attr_br_mis_pred.attr.attr,
- &armv8_event_attr_cpu_cycles.attr.attr,
- &armv8_event_attr_br_pred.attr.attr,
- &armv8_event_attr_mem_access.attr.attr,
- &armv8_event_attr_l1i_cache.attr.attr,
- &armv8_event_attr_l1d_cache_wb.attr.attr,
- &armv8_event_attr_l2d_cache.attr.attr,
- &armv8_event_attr_l2d_cache_refill.attr.attr,
- &armv8_event_attr_l2d_cache_wb.attr.attr,
- &armv8_event_attr_bus_access.attr.attr,
- &armv8_event_attr_memory_error.attr.attr,
- &armv8_event_attr_inst_spec.attr.attr,
- &armv8_event_attr_ttbr_write_retired.attr.attr,
- &armv8_event_attr_bus_cycles.attr.attr,
- &armv8_event_attr_l1d_cache_allocate.attr.attr,
- &armv8_event_attr_l2d_cache_allocate.attr.attr,
- &armv8_event_attr_br_retired.attr.attr,
- &armv8_event_attr_br_mis_pred_retired.attr.attr,
- &armv8_event_attr_stall_frontend.attr.attr,
- &armv8_event_attr_stall_backend.attr.attr,
- &armv8_event_attr_l1d_tlb.attr.attr,
- &armv8_event_attr_l1i_tlb.attr.attr,
- &armv8_event_attr_l2i_cache.attr.attr,
- &armv8_event_attr_l2i_cache_refill.attr.attr,
- &armv8_event_attr_l3d_cache_allocate.attr.attr,
- &armv8_event_attr_l3d_cache_refill.attr.attr,
- &armv8_event_attr_l3d_cache.attr.attr,
- &armv8_event_attr_l3d_cache_wb.attr.attr,
- &armv8_event_attr_l2d_tlb_refill.attr.attr,
- &armv8_event_attr_l2i_tlb_refill.attr.attr,
- &armv8_event_attr_l2d_tlb.attr.attr,
- &armv8_event_attr_l2i_tlb.attr.attr,
- &armv8_event_attr_remote_access.attr.attr,
- &armv8_event_attr_ll_cache.attr.attr,
- &armv8_event_attr_ll_cache_miss.attr.attr,
- &armv8_event_attr_dtlb_walk.attr.attr,
- &armv8_event_attr_itlb_walk.attr.attr,
- &armv8_event_attr_ll_cache_rd.attr.attr,
- &armv8_event_attr_ll_cache_miss_rd.attr.attr,
- &armv8_event_attr_remote_access_rd.attr.attr,
- &armv8_event_attr_sample_pop.attr.attr,
- &armv8_event_attr_sample_feed.attr.attr,
- &armv8_event_attr_sample_filtrate.attr.attr,
- &armv8_event_attr_sample_collision.attr.attr,
+ ARMV8_PMUV3_EVENT_ATTRS
NULL,
};
--
2.17.1
next prev parent reply other threads:[~2019-04-04 23:25 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-04 23:25 [PATCH 0/2] arm64: perf: Expose Cortex-A53 micro architectural events Florian Fainelli
2019-04-04 23:25 ` Florian Fainelli [this message]
2019-04-04 23:25 ` [PATCH 2/2] " Florian Fainelli
2019-04-05 9:36 ` [PATCH 0/2] " Robin Murphy
2019-04-05 12:36 ` Jiri Olsa
2019-04-05 16:14 ` Florian Fainelli
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