From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, acme@kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH 1/2] perf/x86/intel: Support adaptive PEBS for fixed counters
Date: Tue, 9 Apr 2019 18:09:59 -0700 [thread overview]
Message-ID: <1554858600-148296-2-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1554858600-148296-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Fixed counters can also generate adaptive PEBS record, if the
corresponding bit in IA32_FIXED_CTR_CTRL is set.
Otherwise, only basic record is generated.
Unconditionally set the bit when PEBS is enabled on fixed counters.
Let MSR_PEBS_CFG decide which format of PEBS record should be generated.
There is no harmful to leave the bit set.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 5 +++++
arch/x86/include/asm/perf_event.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 56df0f6..f34d92b 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2174,6 +2174,11 @@ static void intel_pmu_enable_fixed(struct perf_event *event)
bits <<= (idx * 4);
mask = 0xfULL << (idx * 4);
+ if (x86_pmu.intel_cap.pebs_baseline && event->attr.precise_ip) {
+ bits |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
+ mask |= ICL_FIXED_0_ADAPTIVE << (idx * 4);
+ }
+
rdmsrl(hwc->config_base, ctrl_val);
ctrl_val &= ~mask;
ctrl_val |= bits;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index dcb8bac..ce0dc88 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -33,6 +33,7 @@
#define HSW_IN_TX (1ULL << 32)
#define HSW_IN_TX_CHECKPOINTED (1ULL << 33)
#define ICL_EVENTSEL_ADAPTIVE (1ULL << 34)
+#define ICL_FIXED_0_ADAPTIVE (1ULL << 32)
#define AMD64_EVENTSEL_INT_CORE_ENABLE (1ULL << 36)
#define AMD64_EVENTSEL_GUESTONLY (1ULL << 40)
--
2.7.4
next prev parent reply other threads:[~2019-04-10 1:10 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 1:09 [PATCH 0/2] perf: Add Tremont support kan.liang
2019-04-10 1:09 ` kan.liang [this message]
2019-04-10 7:41 ` [PATCH 1/2] perf/x86/intel: Support adaptive PEBS for fixed counters Peter Zijlstra
2019-04-10 13:57 ` Liang, Kan
2019-04-10 1:10 ` [PATCH 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang
2019-04-10 7:51 ` Peter Zijlstra
2019-04-10 13:58 ` Liang, Kan
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