From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@redhat.com, linux-kernel@vger.kernel.org
Cc: tglx@linutronix.de, acme@kernel.org, jolsa@kernel.org,
eranian@google.com, alexander.shishkin@linux.intel.com,
ak@linux.intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 1/2] perf/x86/intel: Fix the checking for instruction event
Date: Wed, 10 Apr 2019 11:57:08 -0700 [thread overview]
Message-ID: <1554922629-126287-2-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1554922629-126287-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Some bits must be masked before checking X86_CONFIG(.event=0xc0), e.g.
ARCH_PERFMON_EVENTSEL_INT, ARCH_PERFMON_EVENTSEL_USR and
ARCH_PERFMON_EVENTSEL_OS. Those bits will be set in hw_config().
Otherwise the condition will never be met.
Other fields, e.g the INV, ANY, E, or CMASK fields are not allowed for
the reduced Skid PEBS.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
New patch to fix a bug on top of Icelake V5 patch series
(with Peter's cleanup patch).
The patch may be merged back into:
Subject: perf/x86/intel: Add Icelake support
arch/x86/events/intel/core.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index f34d92b..34220ab 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3421,6 +3421,9 @@ hsw_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
return c;
}
+#define EVENT_CONFIG(config) \
+ (config & (X86_ALL_EVENT_FLAGS | INTEL_ARCH_EVENT_MASK))
+
static struct event_constraint *
icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
struct perf_event *event)
@@ -3430,7 +3433,7 @@ icl_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
* Force instruction:ppp in Fixed counter 0
*/
if ((event->attr.precise_ip == 3) &&
- (event->hw.config == X86_CONFIG(.event=0xc0)))
+ (EVENT_CONFIG(event->hw.config) == X86_CONFIG(.event=0xc0)))
return &fixed_counter0_constraint;
return hsw_get_event_constraints(cpuc, idx, event);
--
2.7.4
next prev parent reply other threads:[~2019-04-10 18:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-04-10 18:57 [PATCH V2 0/2] perf: Add Tremont support kan.liang
2019-04-10 18:57 ` kan.liang [this message]
2019-04-10 18:57 ` [PATCH V2 2/2] perf/x86/intel: Add Tremont core PMU support kan.liang
2019-04-11 9:06 ` Peter Zijlstra
2019-04-11 13:30 ` Liang, Kan
2019-04-11 13:33 ` Peter Zijlstra
2019-04-11 14:13 ` Liang, Kan
2019-04-16 11:41 ` [tip:perf/core] " tip-bot for Kan Liang
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