From: Lukasz Luba <l.luba@partner.samsung.com>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org
Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org,
cw00.choi@samsung.com, kyungmin.park@samsung.com,
m.szyprowski@samsung.com, s.nawrocki@samsung.com,
myungjoo.ham@samsung.com, keescook@chromium.org,
tony@atomide.com, jroedel@suse.de, treding@nvidia.com,
digetx@gmail.com, willy.mh.wolff.ml@gmail.com,
Lukasz Luba <l.luba@partner.samsung.com>
Subject: [PATCH v7 06/13] drivers: memory: extend of_memory by LPDDR3 support
Date: Mon, 6 May 2019 17:11:54 +0200 [thread overview]
Message-ID: <1557155521-30949-7-git-send-email-l.luba@partner.samsung.com> (raw)
In-Reply-To: <1557155521-30949-1-git-send-email-l.luba@partner.samsung.com>
The patch adds AC timings information needed to support LPDDR3 and memory
controllers. The structure is used in of_memory and currently in Exynos
5422 DMC. Add parsing data needed for LPDDR3 support.
It is currently used in Exynos5422 Dynamic Memory Controller.
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
---
drivers/memory/of_memory.c | 148 +++++++++++++++++++++++++++++++++++++++++++++
drivers/memory/of_memory.h | 20 +++++-
include/memory/jedec_ddr.h | 62 +++++++++++++++++++
3 files changed, 229 insertions(+), 1 deletion(-)
diff --git a/drivers/memory/of_memory.c b/drivers/memory/of_memory.c
index 2f5ed73..19fbbcd 100644
--- a/drivers/memory/of_memory.c
+++ b/drivers/memory/of_memory.c
@@ -2,6 +2,7 @@
* OpenFirmware helpers for memory drivers
*
* Copyright (C) 2012 Texas Instruments, Inc.
+ * Copyright (C) 2019 Samsung Electronics Co., Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -152,3 +153,150 @@ const struct lpddr2_timings *of_get_ddr_timings(struct device_node *np_ddr,
return lpddr2_jedec_timings;
}
EXPORT_SYMBOL(of_get_ddr_timings);
+
+/**
+ * of_lpddr3_get_min_tck() - extract min timing values for lpddr3
+ * @np: pointer to ddr device tree node
+ * @device: device requesting for min timing values
+ *
+ * Populates the lpddr3_min_tck structure by extracting data
+ * from device tree node. Returns a pointer to the populated
+ * structure. If any error in populating the structure, returns NULL.
+ */
+const struct lpddr3_min_tck *of_lpddr3_get_min_tck(struct device_node *np,
+ struct device *dev)
+{
+ int ret = 0;
+ struct lpddr3_min_tck *min;
+
+ min = devm_kzalloc(dev, sizeof(*min), GFP_KERNEL);
+ if (!min)
+ goto default_min_tck;
+
+ ret |= of_property_read_u32(np, "tRFC-min-tck", &min->tRFC);
+ ret |= of_property_read_u32(np, "tRRD-min-tck", &min->tRRD);
+ ret |= of_property_read_u32(np, "tRPab-min-tck", &min->tRPab);
+ ret |= of_property_read_u32(np, "tRPpb-min-tck", &min->tRPpb);
+ ret |= of_property_read_u32(np, "tRCD-min-tck", &min->tRCD);
+ ret |= of_property_read_u32(np, "tRC-min-tck", &min->tRC);
+ ret |= of_property_read_u32(np, "tRAS-min-tck", &min->tRAS);
+ ret |= of_property_read_u32(np, "tWTR-min-tck", &min->tWTR);
+ ret |= of_property_read_u32(np, "tWR-min-tck", &min->tWR);
+ ret |= of_property_read_u32(np, "tRTP-min-tck", &min->tRTP);
+ ret |= of_property_read_u32(np, "tW2W-C2C-min-tck", &min->tW2W_C2C);
+ ret |= of_property_read_u32(np, "tR2R-C2C-min-tck", &min->tR2R_C2C);
+ ret |= of_property_read_u32(np, "tWL-min-tck", &min->tWL);
+ ret |= of_property_read_u32(np, "tDQSCK-min-tck", &min->tDQSCK);
+ ret |= of_property_read_u32(np, "tRL-min-tck", &min->tRL);
+ ret |= of_property_read_u32(np, "tFAW-min-tck", &min->tFAW);
+ ret |= of_property_read_u32(np, "tXSR-min-tck", &min->tXSR);
+ ret |= of_property_read_u32(np, "tXP-min-tck", &min->tXP);
+ ret |= of_property_read_u32(np, "tCKE-min-tck", &min->tCKE);
+ ret |= of_property_read_u32(np, "tCKESR-min-tck", &min->tCKESR);
+ ret |= of_property_read_u32(np, "tMRD-min-tck", &min->tMRD);
+
+ if (ret) {
+ dev_warn(dev, "%s: errors while parsing min-tck values\n",
+ __func__);
+ devm_kfree(dev, min);
+ goto default_min_tck;
+ }
+
+ return min;
+
+default_min_tck:
+ dev_warn(dev, "%s: using default min-tck values\n", __func__);
+ return NULL;
+}
+EXPORT_SYMBOL(of_lpddr3_get_min_tck);
+
+static int of_lpddr3_do_get_timings(struct device_node *np,
+ struct lpddr3_timings *tim)
+{
+ int ret;
+
+ /* The 'reg' param required since DT has changed, used as 'max-freq' */
+ ret = of_property_read_u32(np, "reg", &tim->max_freq);
+ ret |= of_property_read_u32(np, "min-freq", &tim->min_freq);
+ ret |= of_property_read_u32(np, "tRFC", &tim->tRFC);
+ ret |= of_property_read_u32(np, "tRRD", &tim->tRRD);
+ ret |= of_property_read_u32(np, "tRPab", &tim->tRPab);
+ ret |= of_property_read_u32(np, "tRPpb", &tim->tRPpb);
+ ret |= of_property_read_u32(np, "tRCD", &tim->tRCD);
+ ret |= of_property_read_u32(np, "tRC", &tim->tRC);
+ ret |= of_property_read_u32(np, "tRAS", &tim->tRAS);
+ ret |= of_property_read_u32(np, "tWTR", &tim->tWTR);
+ ret |= of_property_read_u32(np, "tWR", &tim->tWR);
+ ret |= of_property_read_u32(np, "tRTP", &tim->tRTP);
+ ret |= of_property_read_u32(np, "tW2W-C2C", &tim->tW2W_C2C);
+ ret |= of_property_read_u32(np, "tR2R-C2C", &tim->tR2R_C2C);
+ ret |= of_property_read_u32(np, "tFAW", &tim->tFAW);
+ ret |= of_property_read_u32(np, "tXSR", &tim->tXSR);
+ ret |= of_property_read_u32(np, "tXP", &tim->tXP);
+ ret |= of_property_read_u32(np, "tCKE", &tim->tCKE);
+ ret |= of_property_read_u32(np, "tCKESR", &tim->tCKESR);
+ ret |= of_property_read_u32(np, "tMRD", &tim->tMRD);
+
+ return ret;
+}
+
+/**
+ * of_lpddr3_get_ddr_timings() - extracts the lpddr3 timings and updates no of
+ * frequencies available.
+ * @np_ddr: Pointer to ddr device tree node
+ * @dev: Device requesting for ddr timings
+ * @device_type: Type of ddr
+ * @nr_frequencies: No of frequencies available for ddr
+ * (updated by this function)
+ *
+ * Populates lpddr3_timings structure by extracting data from device
+ * tree node. Returns pointer to populated structure. If any error
+ * while populating, returns NULL.
+ */
+const struct lpddr3_timings *of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
+ struct device *dev, u32 device_type, u32 *nr_frequencies)
+{
+ struct lpddr3_timings *timings = NULL;
+ u32 arr_sz = 0, i = 0;
+ struct device_node *np_tim;
+ char *tim_compat = NULL;
+
+ switch (device_type) {
+ case DDR_TYPE_LPDDR3:
+ tim_compat = "jedec,lpddr3-timings";
+ break;
+ default:
+ dev_warn(dev, "%s: un-supported memory type\n", __func__);
+ }
+
+ for_each_child_of_node(np_ddr, np_tim)
+ if (of_device_is_compatible(np_tim, tim_compat))
+ arr_sz++;
+
+ if (arr_sz)
+ timings = devm_kcalloc(dev, arr_sz, sizeof(*timings),
+ GFP_KERNEL);
+
+ if (!timings)
+ goto default_timings;
+
+ for_each_child_of_node(np_ddr, np_tim) {
+ if (of_device_is_compatible(np_tim, tim_compat)) {
+ if (of_lpddr3_do_get_timings(np_tim, &timings[i])) {
+ devm_kfree(dev, timings);
+ goto default_timings;
+ }
+ i++;
+ }
+ }
+
+ *nr_frequencies = arr_sz;
+
+ return timings;
+
+default_timings:
+ dev_warn(dev, "%s: using default timings\n", __func__);
+ *nr_frequencies = 0;
+ return NULL;
+}
+EXPORT_SYMBOL(of_lpddr3_get_ddr_timings);
diff --git a/drivers/memory/of_memory.h b/drivers/memory/of_memory.h
index ef2514f..8cf2ce6 100644
--- a/drivers/memory/of_memory.h
+++ b/drivers/memory/of_memory.h
@@ -18,6 +18,11 @@ extern const struct lpddr2_min_tck *of_get_min_tck(struct device_node *np,
extern const struct lpddr2_timings
*of_get_ddr_timings(struct device_node *np_ddr, struct device *dev,
u32 device_type, u32 *nr_frequencies);
+extern const struct lpddr3_min_tck
+ *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev);
+extern const struct lpddr3_timings
+ *of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
+ struct device *dev, u32 device_type, u32 *nr_frequencies);
#else
static inline const struct lpddr2_min_tck
*of_get_min_tck(struct device_node *np, struct device *dev)
@@ -31,6 +36,19 @@ static inline const struct lpddr2_timings
{
return NULL;
}
-#endif /* CONFIG_OF && CONFIG_DDR */
+
+static inline const struct lpddr3_min_tck
+ *of_lpddr3_get_min_tck(struct device_node *np, struct device *dev)
+{
+ return NULL;
+}
+
+static inline const struct lpddr3_timings
+ *of_lpddr3_get_ddr_timings(struct device_node *np_ddr,
+ struct device *dev, u32 device_type, u32 *nr_frequencies)
+{
+ return NULL;
+}
+#endif
#endif /* __LINUX_MEMORY_OF_REG_ */
diff --git a/include/memory/jedec_ddr.h b/include/memory/jedec_ddr.h
index ddad0f8..3601825 100644
--- a/include/memory/jedec_ddr.h
+++ b/include/memory/jedec_ddr.h
@@ -32,6 +32,7 @@
#define DDR_TYPE_LPDDR2_S4 3
#define DDR_TYPE_LPDDR2_S2 4
#define DDR_TYPE_LPDDR2_NVM 5
+#define DDR_TYPE_LPDDR3 6
/* DDR IO width */
#define DDR_IO_WIDTH_4 1
@@ -172,4 +173,65 @@ extern const struct lpddr2_timings
lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES];
extern const struct lpddr2_min_tck lpddr2_jedec_min_tck;
+
+/*
+ * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
+ * All parameters are in pico seconds(ps) unless explicitly indicated
+ * with a suffix like tRAS_max_ns below
+ */
+struct lpddr3_timings {
+ u32 max_freq;
+ u32 min_freq;
+ u32 tRFC;
+ u32 tRRD;
+ u32 tRPab;
+ u32 tRPpb;
+ u32 tRCD;
+ u32 tRC;
+ u32 tRAS;
+ u32 tWTR;
+ u32 tWR;
+ u32 tRTP;
+ u32 tW2W_C2C;
+ u32 tR2R_C2C;
+ u32 tWL;
+ u32 tDQSCK;
+ u32 tRL;
+ u32 tFAW;
+ u32 tXSR;
+ u32 tXP;
+ u32 tCKE;
+ u32 tCKESR;
+ u32 tMRD;
+};
+
+/*
+ * Min value for some parameters in terms of number of tCK cycles(nCK)
+ * Please set to zero parameters that are not valid for a given memory
+ * type
+ */
+struct lpddr3_min_tck {
+ u32 tRFC;
+ u32 tRRD;
+ u32 tRPab;
+ u32 tRPpb;
+ u32 tRCD;
+ u32 tRC;
+ u32 tRAS;
+ u32 tWTR;
+ u32 tWR;
+ u32 tRTP;
+ u32 tW2W_C2C;
+ u32 tR2R_C2C;
+ u32 tWL;
+ u32 tDQSCK;
+ u32 tRL;
+ u32 tFAW;
+ u32 tXSR;
+ u32 tXP;
+ u32 tCKE;
+ u32 tCKESR;
+ u32 tMRD;
+};
+
#endif /* __LINUX_JEDEC_DDR_H */
--
2.7.4
next prev parent reply other threads:[~2019-05-06 15:13 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20190506151210eucas1p2c0821ddc691b150725b38398295f8d9b@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 0/13] Exynos5 Dynamic Memory Controller driver Lukasz Luba
[not found] ` <CGME20190506151210eucas1p13c2a4b86a6f987ff34fbe1e2d705fbbf@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 01/13] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Lukasz Luba
2019-05-07 7:33 ` Chanwoo Choi
2019-05-07 8:51 ` Lukasz Luba
2019-05-07 9:17 ` Chanwoo Choi
2019-05-07 9:25 ` Lukasz Luba
[not found] ` <CGME20190506151211eucas1p2d96d7eaa4cda8f8d1787d8f1f1461b9b@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 02/13] clk: samsung: add new clocks for DMC for Exynos5422 SoC Lukasz Luba
2019-05-07 7:36 ` Chanwoo Choi
2019-05-07 8:59 ` Lukasz Luba
[not found] ` <CGME20190506151212eucas1p24110f75fa6ed945f9ae7614fbb8aa13d@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 03/13] clk: samsung: add BPLL rate table for Exynos 5422 SoC Lukasz Luba
2019-05-07 7:36 ` Chanwoo Choi
2019-05-07 9:02 ` Lukasz Luba
[not found] ` <CGME20190506151213eucas1p2ca40029d09ddbbcd11e4a1dd60ae9654@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 04/13] dt-bindings: ddr: rename lpddr2 directory Lukasz Luba
2019-05-07 16:57 ` Rob Herring
2019-05-08 8:31 ` Lukasz Luba
[not found] ` <CGME20190506151214eucas1p17114a7dce506c77ae0bb96b93fd2d838@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 05/13] dt-bindings: ddr: add LPDDR3 memories Lukasz Luba
2019-05-07 17:00 ` Rob Herring
2019-05-08 8:37 ` Lukasz Luba
[not found] ` <CGME20190506151214eucas1p2e87194b1ce66f7184d6770818d02814d@eucas1p2.samsung.com>
2019-05-06 15:11 ` Lukasz Luba [this message]
[not found] ` <CGME20190506151215eucas1p2c57147edac5671c5ec9a223efb6b4adc@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 07/13] dt-bindings: memory-controllers: add Exynos5422 DMC device description Lukasz Luba
2019-05-07 17:04 ` Rob Herring
2019-05-08 7:19 ` Krzysztof Kozlowski
2019-05-08 9:45 ` Lukasz Luba
2019-05-08 10:19 ` Krzysztof Kozlowski
2019-05-08 20:35 ` Rob Herring
2019-05-10 13:12 ` Lukasz Luba
2019-05-08 9:17 ` Lukasz Luba
[not found] ` <CGME20190506151216eucas1p2f0c5ba0920b256789240b87fbb88f3fe@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 08/13] drivers: memory: add DMC driver for Exynos5422 Lukasz Luba
2019-05-08 7:11 ` Krzysztof Kozlowski
2019-05-08 9:32 ` Lukasz Luba
[not found] ` <CGME20190506151217eucas1p2c9348f2766870e7c22c2dabaab5d57a1@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 09/13] drivers: devfreq: events: add Exynos PPMU new events Lukasz Luba
[not found] ` <CGME20190506151218eucas1p1f3bf0b48470595537a893bd0b39e75b7@eucas1p1.samsung.com>
2019-05-06 15:11 ` [PATCH v7 10/13] ARM: dts: exynos: add chipid label and syscon compatible Lukasz Luba
[not found] ` <CGME20190506151219eucas1p2feab00f7b7c1c5fdd5614423fb38eae2@eucas1p2.samsung.com>
2019-05-06 15:11 ` [PATCH v7 11/13] ARM: dts: exynos: add syscon to clock compatible Lukasz Luba
2019-05-08 7:22 ` Krzysztof Kozlowski
2019-05-08 9:50 ` Lukasz Luba
2019-05-08 10:17 ` Krzysztof Kozlowski
2019-05-08 13:13 ` Lukasz Luba
[not found] ` <CGME20190506151219eucas1p2b5c3368873696f51e7d0d3a3e6d6bf1e@eucas1p2.samsung.com>
2019-05-06 15:12 ` [PATCH v7 12/13] ARM: dts: exynos: add DMC device for exynos5422 Lukasz Luba
2019-05-08 7:25 ` Krzysztof Kozlowski
2019-05-08 10:05 ` Lukasz Luba
[not found] ` <CGME20190506151220eucas1p237812f2420594eb651d80cf91076510c@eucas1p2.samsung.com>
2019-05-06 15:12 ` [PATCH v7 13/13] ARM: exynos_defconfig: enable DMC driver Lukasz Luba
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