From: Luwei Kang <luwei.kang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
hpa@zytor.com, x86@kernel.org, pbonzini@redhat.com,
rkrcmar@redhat.com, Luwei Kang <luwei.kang@intel.com>
Subject: [PATCH v1 1/6] x86/fpu: Introduce new fpu state for Intel processor trace
Date: Thu, 16 May 2019 16:25:09 +0800 [thread overview]
Message-ID: <1557995114-21629-2-git-send-email-luwei.kang@intel.com> (raw)
In-Reply-To: <1557995114-21629-1-git-send-email-luwei.kang@intel.com>
Introduce new fpu state structure pt_state to save Intel
processor trace configuration. The upcoming using
XSAVES/XRSTORS to switch the Intel PT configuration
on VM-Entry/Exit will use this structure.
Signed-off-by: Luwei Kang <luwei.kang@intel.com>
---
arch/x86/include/asm/fpu/types.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/x86/include/asm/fpu/types.h b/arch/x86/include/asm/fpu/types.h
index 2e32e17..8cbb42e 100644
--- a/arch/x86/include/asm/fpu/types.h
+++ b/arch/x86/include/asm/fpu/types.h
@@ -221,6 +221,19 @@ struct avx_512_hi16_state {
} __packed;
/*
+ * State component 8 is used for some 64-bit registers
+ * of Intel processor trace.
+ */
+struct pt_state {
+ u64 rtit_ctl;
+ u64 rtit_output_base;
+ u64 rtit_output_mask;
+ u64 rtit_status;
+ u64 rtit_cr3_match;
+ u64 rtit_addrx_ab[0];
+} __packed;
+
+/*
* State component 9: 32-bit PKRU register. The state is
* 8 bytes long but only 4 bytes is used currently.
*/
--
1.8.3.1
next prev parent reply other threads:[~2019-05-16 8:26 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-16 8:25 [PATCH v1 0/6] KVM: VMX: Intel PT configuration switch using XSAVES/XRSTORS on VM-Entry/Exit Luwei Kang
2019-05-16 8:25 ` Luwei Kang [this message]
2019-05-16 8:25 ` [PATCH v1 2/6] KVM: VMX: Reuse the pt_state structure for PT context Luwei Kang
2019-05-16 8:25 ` [PATCH v1 3/6] KVM: VMX: Dymamic allocate Intel PT configuration state Luwei Kang
2019-05-16 8:25 ` [PATCH v1 4/6] KVM: VMX: Allocate XSAVE area for Intel PT configuration Luwei Kang
2019-05-16 8:25 ` [PATCH v1 5/6] KVM: VMX: Intel PT configration context switch using XSAVES/XRSTORS Luwei Kang
2019-05-16 8:25 ` [PATCH v1 6/6] KVM: VMX: Get PT state from xsave area to variables Luwei Kang
2019-11-11 13:28 ` [PATCH v1 0/6] KVM: VMX: Intel PT configuration switch using XSAVES/XRSTORS on VM-Entry/Exit Paolo Bonzini
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