From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: stefan.wahren@i2se.com, Florian Fainelli <f.fainelli@gmail.com>,
Ray Jui <rjui@broadcom.com>,
Scott Branden <sbranden@broadcom.com>,
bcm-kernel-feedback-list@broadcom.com,
Eric Anholt <eric@anholt.net>
Cc: mbrugger@suse.de, viresh.kumar@linaro.org, rjw@rjwysocki.net,
sboyd@kernel.org, ptesarik@suse.com,
linux-rpi-kernel@lists.infradead.org, ssuloev@orpaltech.com,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
mturquette@baylibre.com, linux-pm@vger.kernel.org,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
linux-kernel@vger.kernel.org
Subject: [RFC v2 2/5] clk: bcm2835: set pllb_arm divisor as readonly
Date: Mon, 20 May 2019 12:47:04 +0200 [thread overview]
Message-ID: <20190520104708.11980-3-nsaenzjulienne@suse.de> (raw)
In-Reply-To: <20190520104708.11980-1-nsaenzjulienne@suse.de>
This divisor is controlled by the firmware, we don't want the clock
subsystem to update it inadvertently.
Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
---
drivers/clk/bcm/clk-bcm2835.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index c2772dfb155a..5aea110672f3 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -465,6 +465,7 @@ struct bcm2835_pll_divider_data {
u32 hold_mask;
u32 fixed_divider;
u32 flags;
+ u32 div_flags;
};
struct bcm2835_clock_data {
@@ -1349,7 +1350,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
divider->div.reg = cprman->regs + data->a2w_reg;
divider->div.shift = A2W_PLL_DIV_SHIFT;
divider->div.width = A2W_PLL_DIV_BITS;
- divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
+ divider->div.flags = data->div_flags | CLK_DIVIDER_MAX_AT_ZERO;
divider->div.lock = &cprman->regs_lock;
divider->div.hw.init = &init;
divider->div.table = NULL;
@@ -1676,7 +1677,8 @@ static const struct bcm2835_clk_desc clk_desc_array[] = {
.load_mask = CM_PLLB_LOADARM,
.hold_mask = CM_PLLB_HOLDARM,
.fixed_divider = 1,
- .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .div_flags = CLK_DIVIDER_READ_ONLY),
/*
* PLLC is the core PLL, used to drive the core VPU clock.
--
2.21.0
next prev parent reply other threads:[~2019-05-20 10:47 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-05-20 10:47 [RFC v2 0/5] cpufreq support for the Raspberry Pi Nicolas Saenz Julienne
2019-05-20 10:47 ` [RFC v2 1/5] clk: bcm2835: set CLK_GET_RATE_NOCACHE on CPU clocks Nicolas Saenz Julienne
2019-05-20 11:42 ` Stefan Wahren
2019-05-20 10:47 ` Nicolas Saenz Julienne [this message]
2019-05-20 11:43 ` [RFC v2 2/5] clk: bcm2835: set pllb_arm divisor as readonly Stefan Wahren
2019-05-20 10:47 ` [RFC v2 3/5] clk: bcm2835: use firmware interface to update pllb Nicolas Saenz Julienne
2019-05-20 12:11 ` Stefan Wahren
2019-05-20 12:14 ` Stefan Wahren
2019-05-21 12:40 ` Stefan Wahren
2019-05-21 15:47 ` Nicolas Saenz Julienne
2019-05-21 21:43 ` Stefan Wahren
2019-05-23 8:51 ` Nicolas Saenz Julienne
2019-05-20 12:43 ` Oliver Neukum
2019-05-21 11:39 ` Nicolas Saenz Julienne
2019-05-21 12:14 ` Petr Tesarik
2019-05-21 12:18 ` Nicolas Saenz Julienne
2019-05-20 10:47 ` [RFC v2 4/5] dts: bcm2837: add per-cpu clock devices Nicolas Saenz Julienne
2019-05-20 12:19 ` Stefan Wahren
2019-05-21 11:40 ` Nicolas Saenz Julienne
2019-05-20 10:47 ` [RFC v2 5/5] cpufreq: add driver for Raspbery Pi Nicolas Saenz Julienne
2019-05-20 10:51 ` Viresh Kumar
2019-05-20 12:30 ` Stefan Wahren
2019-05-20 10:51 ` [RFC v2 0/5] cpufreq support for the Raspberry Pi Viresh Kumar
2019-05-21 12:02 ` Nicolas Saenz Julienne
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